From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17596 invoked by alias); 27 Feb 2008 13:19:37 -0000 Received: (qmail 17586 invoked by uid 22791); 27 Feb 2008 13:19:36 -0000 X-Spam-Check-By: sourceware.org Received: from NaN.false.org (HELO nan.false.org) (208.75.86.248) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 27 Feb 2008 13:19:12 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 1E63398140; Wed, 27 Feb 2008 13:19:11 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 002669811F; Wed, 27 Feb 2008 13:19:10 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1JUMBi-0005vo-Bu; Wed, 27 Feb 2008 08:19:10 -0500 Date: Wed, 27 Feb 2008 13:20:00 -0000 From: Daniel Jacobowitz To: Ulrich Weigand Cc: gdb-patches@sourceware.org Subject: Re: [rfc][3/3] gdbserver bi-arch for ppc: enable bi-arch support Message-ID: <20080227131910.GC21538@caradoc.them.org> Mail-Followup-To: Ulrich Weigand , gdb-patches@sourceware.org References: <200802080111.m181BMCL008752@d12av02.megacenter.de.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200802080111.m181BMCL008752@d12av02.megacenter.de.ibm.com> User-Agent: Mutt/1.5.17 (2007-12-11) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-02/txt/msg00431.txt.bz2 On Fri, Feb 08, 2008 at 02:11:22AM +0100, Ulrich Weigand wrote: > + /* Only if the high bit of the MSR is set, we actually have > + a 64-bit inferior. */ > +#ifdef __ALTIVEC__ > + collect_register_by_name ("msr", &msr); > +#else > + collect_register_by_name ("ps", &msr); > +#endif > + if (msr < 0) > + return; > +#endif This #ifdef can go away; in the manually written regformats files, calls to collect_register_by_name are the only thing that rely on the register name, so you could just rename it to msr. Otherwise OK. > + /* OK, we have a 32-bit inferior. */ > +#ifdef __ALTIVEC__ > + init_registers_powerpc_32 (); > +#else > +#ifdef __SPE__ > + init_registers_powerpc_e500 (); > +#else > + init_registers_ppc (); > +#endif > +#endif I hope we can autodetect AltiVec and SPE too... Maybe we have to resort to checking the inferior's auxv? -- Daniel Jacobowitz CodeSourcery