From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24239 invoked by alias); 6 Feb 2008 04:42:03 -0000 Received: (qmail 24231 invoked by uid 22791); 6 Feb 2008 04:42:02 -0000 X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 06 Feb 2008 04:41:45 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id m164fhIc031672; Tue, 5 Feb 2008 23:41:43 -0500 Received: from post-office.corp.redhat.com (post-office.corp.redhat.com [10.11.254.111]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id m164fhhf023333; Tue, 5 Feb 2008 23:41:43 -0500 Received: from greed.delorie.com (vpn-14-4.rdu.redhat.com [10.11.14.4]) by post-office.corp.redhat.com (8.13.8/8.13.8) with ESMTP id m164fgd3009755; Tue, 5 Feb 2008 23:41:42 -0500 Received: from greed.delorie.com (greed.delorie.com [127.0.0.1]) by greed.delorie.com (8.13.8/8.13.8) with ESMTP id m164fgqs003536; Tue, 5 Feb 2008 23:41:42 -0500 Received: (from dj@localhost) by greed.delorie.com (8.13.8/8.13.8/Submit) id m164fgOS003533; Tue, 5 Feb 2008 23:41:42 -0500 Date: Wed, 06 Feb 2008 04:42:00 -0000 Message-Id: <200802060441.m164fgOS003533@greed.delorie.com> From: DJ Delorie To: hp@bitrange.com CC: gdb-patches@sourceware.org In-reply-to: <20080205214541.U96204@dair.pair.com> (message from Hans-Peter Nilsson on Tue, 5 Feb 2008 21:53:07 -0500 (EST)) Subject: Re: FAIL: v850 divh.cgs (Re: [v850 sim] Fix div, shift, sat, bsh opcodes, add initial testsuite) References: <200802060040.m160eC0X030643@greed.delorie.com> <20080205214541.U96204@dair.pair.com> X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-02/txt/msg00123.txt.bz2 > Perhaps the code isn't 64-bit-clean? I think, in general, the v850 sim won't be 64-bit clean, but I did at least clean up the opcodes we're testing so far. * simops.c (OP_1C007E0): Compensate for 64 bit hosts. (OP_18007E0): Likewise. (OP_2C007E0): Likewise. (OP_28007E0): Likewise. * v850.igen (divh): Likewise. Index: simops.c =================================================================== RCS file: /cvs/src/src/sim/v850/simops.c,v retrieving revision 1.9 diff -p -U3 -r1.9 simops.c --- simops.c 6 Feb 2008 00:40:05 -0000 1.9 +++ simops.c 6 Feb 2008 04:38:31 -0000 @@ -2209,8 +2209,8 @@ OP_1C007E0 (void) imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); - divide_by = State.regs[ OP[0] ]; - divide_this = State.regs[ OP[1] ] << imm5; + divide_by = (signed32) State.regs[ OP[0] ]; + divide_this = (signed32) (State.regs[ OP[1] ] << imm5); divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); @@ -2280,7 +2280,7 @@ OP_18007E0 (void) imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); divide_by = EXTEND16 (State.regs[ OP[0] ]); - divide_this = State.regs[ OP[1] ] << imm5; + divide_this = (signed32) (State.regs[ OP[1] ] << imm5); divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); @@ -2351,14 +2351,14 @@ OP_2C007E0 (void) /* Compute the result. */ - divide_by = State.regs[ OP[0] ]; + divide_by = (signed32) State.regs[ OP[0] ]; divide_this = State.regs[ OP[1] ]; if (divide_by == 0) { PSW |= PSW_OV; } - else if (divide_by == -1 && divide_this == (1 << 31)) + else if (divide_by == -1 && divide_this == (1L << 31)) { PSW &= ~PSW_Z; PSW |= PSW_OV | PSW_S; @@ -2367,9 +2367,10 @@ OP_2C007E0 (void) } else { + divide_this = (signed32) divide_this; State.regs[ OP[1] ] = quotient = divide_this / divide_by; State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; - + /* Set condition codes. */ PSW &= ~(PSW_Z | PSW_S | PSW_OV); @@ -2442,7 +2443,7 @@ OP_28007E0 (void) { PSW |= PSW_OV; } - else if (divide_by == -1 && divide_this == (1 << 31)) + else if (divide_by == -1 && divide_this == (1L << 31)) { PSW &= ~PSW_Z; PSW |= PSW_OV | PSW_S; @@ -2451,6 +2452,7 @@ OP_28007E0 (void) } else { + divide_this = (signed32) divide_this; State.regs[ OP[1] ] = quotient = divide_this / divide_by; State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; Index: v850.igen =================================================================== RCS file: /cvs/src/src/sim/v850/v850.igen,v retrieving revision 1.8 diff -p -U3 -r1.8 v850.igen --- v850.igen 6 Feb 2008 00:40:05 -0000 1.8 +++ v850.igen 6 Feb 2008 04:38:31 -0000 @@ -356,7 +356,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh op0 = EXTEND16 (State.regs[OP[0]]); op1 = State.regs[OP[1]]; - if (op0 == 0xffffffff && op1 == 0x80000000) + if (op0 == -1 && op1 == 0x80000000) { PSW &= ~PSW_Z; PSW |= PSW_OV | PSW_S; @@ -368,7 +368,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh } else { - result = op1 / op0; + result = (signed32) op1 / op0; ov = 0; /* Compute the condition codes. */