From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13334 invoked by alias); 22 Oct 2007 12:09:32 -0000 Received: (qmail 13325 invoked by uid 22791); 22 Oct 2007 12:09:31 -0000 X-Spam-Check-By: sourceware.org Received: from relay01.mx.bawue.net (HELO relay01.mx.bawue.net) (193.7.176.67) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 22 Oct 2007 12:09:25 +0000 Received: from lagash (intrt.mips-uk.com [194.74.144.130]) by relay01.mx.bawue.net (Postfix) with ESMTP id 1D32648D87; Mon, 22 Oct 2007 14:05:24 +0200 (CEST) Received: from ths by lagash with local (Exim 4.68) (envelope-from ) id 1Ijw5u-0004AN-9D; Mon, 22 Oct 2007 13:09:18 +0100 Date: Mon, 22 Oct 2007 13:42:00 -0000 From: Thiemo Seufer To: gdb-patches@sourceware.org, rsandifo@nildram.co.uk Subject: Re: MIPS32R2 simulator fixes Message-ID: <20071022120918.GB25397@networkno.de> References: <87sl43v2ls.fsf@firetop.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87sl43v2ls.fsf@firetop.home> User-Agent: Mutt/1.5.16 (2007-06-11) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00501.txt.bz2 Richard Sandiford wrote: > When extending GCC's -mpaired-single support to MIPS32R2, I noticed > that many of the instructions weren't simulated correctly for > mipsisa32r2-elfoabi: > > - Most of the instructions that are implemented by MIPS32R2 targets > with a 64-bit FPU have the requisite "*mips32r2" marker, but their > filter is "64,f" rather than "32,f". ("32" and "64" are the word > size, not the FPU size.) > > - 64-bit loads and stores need to use do_load_double and > do_store_double for 32-bit targets. > > - SDXC1 and SUXC1 weren't implemented for MIPS32R2. > > - The MIPS32R2 version of check_fmt_p checks UX and PX, but those > flags are always read as 0 on MIPS32R2 targets. There isn't > AFAIK any way of turning off paired-single instructions when > using a MIPS32R2 target that has a 64-bit FPU. It is correct that there's no separate switch to disable paired single when the MIPS-3D ASE is implemented. There is, however, the 3D bit in FCR0 which announces the availablity of paired single instructions, it should be set for the MIPS32R2/MIPS64* emulations. > (check_fmt_p > doesn't need to check that the 64-bit FPU is in 64-bit mode; > that's done elsewhere.) > > - LUXC1 and SUXC1 are unpredictable when the FPU is not in 64-bit mode. > (True for MIPS64 as well as MIPS32, and unpredictability is ignored > for MIPS V.) > > Note that mips*-sde-elf* uses mips64r2, so users of that configuration > wouldn't have come across the first four problems. > > Tested with GCC on mipsisa32r2-elfoabi and mipsisa64r2-elfoabi. > OK to install? > > Richard > > > sim/mips/ > * mips.igen (check_fmt_p): Provide a separate mips32r2 definition > that unconditionally allows fmt_ps. > (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) > (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) > (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change > filter from 64,f to 32,f. > (PREFX): Change filter from 64 to 32. > (LDXC1, LUXC1): Provide separate mips32r2 implementations > that use do_load_double instead of do_load. Make both LUXC1 > versions unpredictable if SizeFGR () != 64. > (SDXC1, SUXC1): Extend to mips32r2, using do_store_double > instead of do_store. Remove unused variable. Make both SUXC1 > versions unpredictable if SizeFGR () != 64. Looks good. Thiemo