Re: [rfc] Target-described register support for MIPS

Maciej W. Rozycki
2007-06-12T18:14:42Z

On Mon, 21 May 2007, Daniel Jacobowitz wrote:

> Maciej, I copied you in case you see anything obviously wrong with my
> choices of required registers, et cetera. You may not be familiar
> with the protocol extensions and so forth I've added for target
> descriptions - it's been my pet project for the last year or two - but
> this is something that I hope would be very useful for MIPS. Could
> you look it over? Additional information about the feature is already
> in the manual; this is just the MIPS-specific support.

Sorry about the delay -- my time constraints are very tight these days.
Here are some comments, but I have only had a brief look over your changes
and certainly not even attempted to try them at the run time.

> +/* Aliases for o32 and most other ABIs. */
> +const struct register_alias mips_o32_aliases[] = {
> + { "ta0", 12 },
> + { "ta1", 13 },
> + { "ta2", 14 },
> + { "ta3", 15 }
> +};

Hmm, these look wrong -- no "ta" registers have been defined for old
ABIs.

> + /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
> + backend is not prepared for that, though. */

I do certainly have some patches covering this area -- please check with
me before commencing any related work. There are quite a lot of FPU
configurations to handle too, including MIPS32r2 processors with 64-bit
FPU and MIPS16 code using hard float.

> Index: gdb/features/mips64-cp0.xml
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ gdb/features/mips64-cp0.xml 2007-05-18 12:01:07.000000000 -0400
> @@ -0,0 +1,13 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2007 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +
> +<feature name="org.gnu.gdb.mips.cp0">
> + <reg name="status" bitsize="64" regnum="32"/>
> + <reg name="badvaddr" bitsize="64" regnum="35"/>
> + <reg name="cause" bitsize="64" regnum="36"/>
> +</feature>

Hmm, "status" and "cause" are generally 32-bit -- for the MIPS64
architecture dmfc0/dmtc0 on such registers are defined as yielding
unpredictable results (and I think at least one implementer did take this
seriously), so they should be accessed as 32-bit registers. For legacy
chips the results may vary too. The cause register is 64-bit for the
R8000 IIRC, but whether it matters should probably be verified by an IRIX
user.

These are just minor nits. Overall I like the change, though to cover
all the optional subsets of cp0 that MIPS32 and MIPS64 specs define quite
a lot of DTDs will have to be created.

Maciej