From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19101 invoked by alias); 12 Jun 2007 18:25:13 -0000 Received: (qmail 19084 invoked by uid 22791); 12 Jun 2007 18:25:12 -0000 X-Spam-Check-By: sourceware.org Received: from NaN.false.org (HELO nan.false.org) (208.75.86.248) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 12 Jun 2007 18:25:07 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 6BFAF982DE; Tue, 12 Jun 2007 18:25:04 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id D32AA982DC; Tue, 12 Jun 2007 18:25:03 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.67) (envelope-from ) id 1HyB3N-0003La-Vg; Tue, 12 Jun 2007 14:25:17 -0400 Date: Tue, 12 Jun 2007 18:25:00 -0000 From: Daniel Jacobowitz To: "Maciej W. Rozycki" Cc: gdb-patches@sourceware.org Subject: Re: [rfc] Target-described register support for MIPS Message-ID: <20070612182517.GA12526@caradoc.them.org> Mail-Followup-To: "Maciej W. Rozycki" , gdb-patches@sourceware.org References: <20070521133939.GA8161@caradoc.them.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.15 (2007-04-09) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-06/txt/msg00205.txt.bz2 On Tue, Jun 12, 2007 at 07:14:29PM +0100, Maciej W. Rozycki wrote: > > +/* Aliases for o32 and most other ABIs. */ > > +const struct register_alias mips_o32_aliases[] = { > > + { "ta0", 12 }, > > + { "ta1", 13 }, > > + { "ta2", 14 }, > > + { "ta3", 15 } > > +}; > > Hmm, these look wrong -- no "ta" registers have been defined for old > ABIs. OK, I'll drop them. They came from O32_SYMBOLIC_REGISTER_NAMES in gas/config/tc-mips.c. > > + /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS > > + backend is not prepared for that, though. */ > > I do certainly have some patches covering this area -- please check with > me before commencing any related work. There are quite a lot of FPU > configurations to handle too, including MIPS32r2 processors with 64-bit > FPU and MIPS16 code using hard float. Great. I'm not planning to work on it right now, but I expect I'll be back. > > + > > + > > + > > + > > + > > Hmm, "status" and "cause" are generally 32-bit -- for the MIPS64 > architecture dmfc0/dmtc0 on such registers are defined as yielding > unpredictable results (and I think at least one implementer did take this > seriously), so they should be accessed as 32-bit registers. For legacy > chips the results may vary too. The cause register is 64-bit for the > R8000 IIRC, but whether it matters should probably be verified by an IRIX > user. Hmm. I only marked them 64-bit because (the manual wasn't entirely clear and) that's how big they were in GDB previously. We can allow 32-bit registers here, but it will take some surgery in the rest of mips-tdep.c. Fortunately it's not an incompatible change, so I hope you'll forgive me for putting it off. > These are just minor nits. Overall I like the change, though to cover > all the optional subsets of cp0 that MIPS32 and MIPS64 specs define quite > a lot of DTDs will have to be created. (documents, not DTDs.) Yes, probably. It may be that there's a more sensible way to define the subsets of cp0; they may all go in a "cp0" feature, and then let GDB determine the available subsets based on which registers are included. When you have a chance to look at it closer, we can work something out - I don't know enough about it. -- Daniel Jacobowitz CodeSourcery