From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8440 invoked by alias); 12 Jun 2007 15:05:06 -0000 Received: (qmail 8430 invoked by uid 22791); 12 Jun 2007 15:05:06 -0000 X-Spam-Check-By: sourceware.org Received: from NaN.false.org (HELO nan.false.org) (208.75.86.248) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 12 Jun 2007 15:05:03 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 25B6A982F1; Tue, 12 Jun 2007 15:05:01 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id A0096982DC; Tue, 12 Jun 2007 15:05:00 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.67) (envelope-from ) id 1Hy7vn-0000Kx-6x; Tue, 12 Jun 2007 11:05:15 -0400 Date: Tue, 12 Jun 2007 15:05:00 -0000 From: Daniel Jacobowitz To: "Maciej W. Rozycki" Cc: Ulrich Weigand , gdb-patches@sourceware.org Subject: Re: [rfc][4/13] Eliminate read_register: read_register in deprecated_mips_set_processor_regs_hack Message-ID: <20070612150515.GB28746@caradoc.them.org> Mail-Followup-To: "Maciej W. Rozycki" , Ulrich Weigand , gdb-patches@sourceware.org References: <200706072058.l57KwV3u019800@d12av02.megacenter.de.ibm.com> <20070612142003.GG7815@caradoc.them.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.15 (2007-04-09) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-06/txt/msg00176.txt.bz2 On Tue, Jun 12, 2007 at 03:49:57PM +0100, Maciej W. Rozycki wrote: > Worse yet -- the approach that we have taken is generic. We can handle > arbitrary MIPS32/MIPS64 processors as conforming to the current revisions > of the base architecture specs and the application-specific extensions > (ASEs) by decoding feature bits defined in cp0 config registers -- there > four config registers defined so far; additional registers may need to be > read for variable length register subsets (e.g. watch and performance > counter registers). I see - that sounds pretty nice; we just need to come up with a way to support it in the rest of GDB. Perhaps we should simply bite the bullet and have a late target description hook in addition to the early one. We can't do without the early one; I added it e.g. for existing MIPS remote targets, where the stub might send back 32-bit or 64-bit registers. Or maybe I'm barking up the wrong tree entirely and we need more than just a target description. The description could report which registers are available and how big they are, and then GDB could gather other details from the config registers. > > I don't have an easy answer for this. Simplest would be to keep it > > local to remote-mips.c (as it currently is), but change how it works; > > move it from common_open to a new remote_mips_read_description, fetch > > the PRID without going through GDB's register cache at all, and then > > create an appropriate target description which specifies the processor > > based on the PRID. It would be nicer if we could make it work for > > remote.c too though. > > Well, it's actually in mips-tdep.c, so it should work for any MIPS > target. Have you moved the call? Right now, that function is only reached through remote-mips.c. > I guess this is unfeasible -- there are too many possibilites which are > neither fixed nor easy to predict as you can see from the above. Unless > the XML tags provide means for subsetting the architecture. Please note > that to make the matter more exciting the subsets do overlap. The XML tags provide whatever you want them to - it's very easy to add new ones :-) We could provide the values of the config registers directly in a description, for instance, and let mips-tdep.c interpret them there. But it might be better to have GDB query them using normal register methods. -- Daniel Jacobowitz CodeSourcery