Re: [RFC] "single step" atomic instruction sequences as a whole on PPC

Luis Machado
2007-05-10T00:48:49Z

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> I'd just do "opcode = insn >> 26" same as in rs6000_software_single_step.
> (In fact I'm wondering why branch_dest doesn't just that for itself ...).

Follows the updated patch. The "opcode" variable is now being assigned
the correct instruction's opcode value (only the corresponding bits).

As a consequence of this change, i've noticed problems with branch
instructions next to the stwcx/stdcx instructions (the end of the
sequence). Getting the destination address of this type of branch could
potentially (upon a failing branch condition) lead to the function
placing a breakpoint right at the stwcx/stdcx instruction, thus leading
us back to the same locking problem.

The variable "closing_insn" was created to check if the breakpoint at
the branch instruction's destination is right at the stwcx/stdcx
instruction. If so, ignore this breakpoint and consider only the
breakpoint after the closing of the atomic sequence.

Regards,
Luis

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2007-05-09 Luis Machado <luisgpm@br.ibm.com>

* rs6000-tdep.c: (deal_with_atomic_sequence) Stores branch instruction's
opcode in the "opcode" variable and declares new variable "closing_insn".

Index: gdb/rs6000-tdep.c
===================================================================
--- gdb.orig/rs6000-tdep.c 2007-05-09 12:19:29.000000000 -0700
+++ gdb/rs6000-tdep.c 2007-05-09 17:36:13.000000000 -0700
@@ -729,12 +729,13 @@
CORE_ADDR breaks[2] = {-1, -1};
CORE_ADDR loc = pc;
CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
+ CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
int insn = read_memory_integer (loc, PPC_INSN_SIZE);
int insn_count;
int index;
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
- const int opcode = BC_INSTRUCTION; /* Branch instruction's OPcode. */
+ int opcode; /* Branch instruction's OPcode. */
int bc_insn_count = 0; /* Conditional branch instruction count. */

/* Assume all atomic sequences start with a lwarx/ldarx instruction. */
@@ -758,6 +759,7 @@
return 0; /* More than one conditional branch found, fallback
to the standard single-step code. */

+ opcode = insn >> 26;
branch_bp = branch_dest (opcode, insn, pc, breaks[0]);

if (branch_bp != -1)
@@ -778,14 +780,19 @@
&& (insn & STWCX_MASK) != STDCX_INSTRUCTION)
return 0;

+ closing_insn = loc;
loc += PPC_INSN_SIZE;
insn = read_memory_integer (loc, PPC_INSN_SIZE);

/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;

- /* Check for duplicated breakpoints. */
- if (last_breakpoint && (breaks[1] == breaks[0]))
+ /* Check for duplicated breakpoints. Check also for a breakpoint
+ placed (branch instruction's destination) at the stwcx/stdcx
+ instruction, this resets the reservation and take us back to the
+ lwarx/ldarx instruction at the beginning of the atomic sequence. */
+ if (last_breakpoint && ((breaks[1] == breaks[0])
+ || (breaks[1] == closing_insn)))
last_breakpoint = 0;

/* Effectively inserts the breakpoints. */