From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23014 invoked by alias); 19 Feb 2007 17:39:35 -0000 Received: (qmail 23003 invoked by uid 22791); 19 Feb 2007 17:39:34 -0000 X-Spam-Check-By: sourceware.org Received: from phoenix.bawue.net (HELO mail.bawue.net) (193.7.176.60) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 19 Feb 2007 17:39:21 +0000 Received: from lagash (intrt.mips-uk.com [194.74.144.130]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bawue.net (Postfix) with ESMTP id 12C46B81B2 for ; Mon, 19 Feb 2007 18:39:19 +0100 (CET) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1HJCVm-0007jp-4U for gdb-patches@sources.redhat.com; Mon, 19 Feb 2007 17:41:14 +0000 Date: Mon, 19 Feb 2007 17:39:00 -0000 To: gdb-patches@sources.redhat.com Subject: [PATCH] MIPS sim: Emulate more of the CP0 config registers Message-ID: <20070219174114.GG1857@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.13 (2006-08-11) From: Thiemo Seufer X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-02/txt/msg00233.txt.bz2 Hello All, I applied the appended patch, it emulates more of the CP0 Config* registers. This allows software to autodetect more of the implemented sim features. Thiemo 2007-02-19 Thiemo Seufer Nigel Stephens (ColdReset): Set CP0 Config0 to reflect the address size supported by this simulator. (decode_coproc): Recognise additional CP0 Config registers correctly. Index: head/sim/mips/interp.c =================================================================== RCS file: /cvs/src/src/sim/mips/interp.c,v retrieving revision 1.19 diff -u -p -r1.19 interp.c --- head/sim/mips/interp.c 12 May 2004 01:42:33 -0000 1.19 +++ head/sim/mips/interp.c 24 Nov 2006 13:32:30 -0000 @@ -1641,6 +1645,20 @@ ColdReset (SIM_DESC sd) FPR_STATE[rn] = fmt_uninterpreted; } + /* Initialise the Config0 register. */ + C0_CONFIG = 0x80000000 /* Config1 present */ + | 2; /* KSEG0 uncached */ + if (WITH_TARGET_WORD_BITSIZE == 64) + { + /* FIXME Currently mips/sim-main.c:address_translation() + truncates all addresses to 32-bits. */ + if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64) + C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */ + else + C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */ + } + if (BigEndianMem) + C0_CONFIG |= 0x00008000; /* Big Endian */ } } @@ -2140,10 +2158,11 @@ decode_coproc (SIM_DESC sd, #else /* 16 = Config R4000 VR4100 VR4300 */ case 16: - if (code == 0x00) - GPR[rt] = C0_CONFIG; - else - C0_CONFIG = GPR[rt]; + if (code == 0x00) + GPR[rt] = C0_CONFIG; + else + /* only bottom three bits are writable */ + C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7); break; #endif #ifdef SUBTARGET_R3900 @@ -2184,6 +2203,40 @@ decode_coproc (SIM_DESC sd, #endif } } + else if ((code == 0x00 || code == 0x01) + && rd == 16) + { + /* [D]MFC0 RT,C0_CONFIG,SEL */ + signed32 cfg = 0; + switch (tail & 0x07) + { + case 0: + cfg = C0_CONFIG; + break; + case 1: + /* MIPS32 r/o Config1: + Config2 present */ + cfg = 0x80000000; + /* MIPS16 implemented. + XXX How to check configuration? */ + cfg |= 0x0000004; + if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) + /* MDMX & FPU implemented */ + cfg |= 0x00000021; + break; + case 2: + /* MIPS32 r/o Config2: + Config3 present. */ + cfg = 0x80000000; + break; + case 3: + /* MIPS32 r/o Config3: + SmartMIPS implemented. */ + cfg = 0x00000002; + break; + } + GPR[rt] = cfg; + } else if (code == 0x10 && (tail & 0x3f) == 0x18) { /* ERET */