Re: [PATCH] Fix PPC non-CFI + CFI unwinding (incomplete in HEAD)

[Daniel Jacobowitz <drow@false.org>]

On Sun, Jan 14, 2007 at 10:34:14PM +0100, Jan Kratochvil wrote:
> On Sat, 13 Jan 2007 17:40:28 +0100, Daniel Jacobowitz wrote:
> ...
> > I was thinking of this:
> >   http://sourceware.org/ml/gdb-patches/2004-12/msg00249.html
> >   http://sourceware.org/ml/gdb-patches/2005-06/msg00242.html
> > 
> > I think someone needs to combine Joel's and Jan's patches.  Joel's is
> > nicer in that it uses branch_dest and the right mask for blrl; Jan's
> > is nicer in that it checks whether lr was saved or is now lost.
> 
> Attached for:
> 	http://sourceware.org/ml/gdb-patches/2004-12/msg00249.html
> and it does not handle in any way
> 	http://sourceware.org/ml/gdb-patches/2005-06/msg00242.html
> as it would be IMO more appropriate to base it on the called code content but
> "I do not have that Darwin code".

I tried combining them myself.  Could you let me know if this patch
still fixes your bug?


-- 
Daniel Jacobowitz
CodeSourcery

2007-01-14  Joel Brobecker  <brobecker@gnat.com>
	    Jan Kratochvil  <jan.kratochvil@redhat.com>
	    Daniel Jacobowitz  <dan@codesourcery.com>

	* rs6000-tdep.c (bl_to_blrl_insn_p): New function.
	(skip_prologue): Allow bl->blrl used by PIC code.

Index: rs6000-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/rs6000-tdep.c,v
retrieving revision 1.260
diff -u -p -r1.260 rs6000-tdep.c
--- rs6000-tdep.c	9 Jan 2007 17:58:57 -0000	1.260
+++ rs6000-tdep.c	20 Jan 2007 19:55:58 -0000
@@ -902,6 +902,30 @@ store_param_on_stack_p (unsigned long op
   return 0;
 }
 
+/* Assuming that INSN is a "bl" instruction located at PC, return
+   nonzero if the destination of the branch is a "blrl" instruction.
+   
+   This sequence is sometimes found in certain function prologues.
+   It allows the function to load the LR register with a value that
+   they can use to access PIC data using PC-relative offsets.  */
+
+static int
+bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
+{
+  const int opcode = 18;
+  const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1);
+  int dest_insn;
+
+  if (dest == -1)
+    return 0;  /* Should never happen, but just return zero to be safe.  */
+  
+  dest_insn = read_memory_integer (dest, 4);
+  if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
+    return 1;
+
+  return 0;
+}
+
 static CORE_ADDR
 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
 {
@@ -1133,6 +1157,12 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR l
 				   to save fprs??? */
 
 	  fdata->frameless = 0;
+
+	  /* If the return address has already been saved, we can skip
+	     calls to blrl (for PIC).  */
+          if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
+	    continue;
+
 	  /* Don't skip over the subroutine call if it is not within
 	     the first three instructions of the prologue and either
 	     we have no line table information or the line info tells