From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18411 invoked by alias); 8 Apr 2006 17:38:23 -0000 Received: (qmail 18362 invoked by uid 22791); 8 Apr 2006 17:38:22 -0000 X-Spam-Check-By: sourceware.org Received: from miranda.se.axis.com (HELO miranda.se.axis.com) (193.13.178.8) by sourceware.org (qpsmtpd/0.31) with ESMTP; Sat, 08 Apr 2006 17:38:20 +0000 Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.83.5.18]) by miranda.se.axis.com (8.12.9/8.12.9/Debian-5local0.1) with ESMTP id k38HcGag016439; Sat, 8 Apr 2006 19:38:16 +0200 Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id k38HcGi5025576; Sat, 8 Apr 2006 19:38:16 +0200 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id k38HcGq1025572; Sat, 8 Apr 2006 19:38:16 +0200 Date: Sat, 08 Apr 2006 17:38:00 -0000 Message-Id: <200604081738.k38HcGq1025572@ignucius.se.axis.com> From: Hans-Peter Nilsson To: gdb-patches@sourceware.org Subject: Committed, sim/cris: correct interrupt-preparation sequence for v32. Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2006-04/txt/msg00094.txt.bz2 Stupid copy-paste-bug; when copying the interrupt-preparation code from the (local-only) SID port, I missed the part to actually set CCS to the calculated new value. sim/testsuite: * sim/cris/hw/rv-n-cris/irq6.ms: New test. sim: * cris/crisv32f.c (MY (deliver_interrupt)): Set CCS to new_ccs. Index: sim/cris/hw/rv-n-cris/irq6.ms =================================================================== RCS file: sim/cris/hw/rv-n-cris/irq6.ms diff -N sim/cris/hw/rv-n-cris/irq6.ms --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/cris/hw/rv-n-cris/irq6.ms 8 Apr 2006 17:31:10 -0000 @@ -0,0 +1,99 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: IRQ 0x8\n +#output: /rv: := 0xeeff4455\n +#output: /rv: REG R 0xd0000034\n +#output: /rv: := 0xdd001122\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0xaaeeff44\n +#output: /rv: REG R 0xd000003c\n +#output: /rv: := 0xff445511\n +#output: pass\n + +# Test two successive ints; that flags are disabled when an interrupt +# is taken, and then automatically (or by register restore) enabled at +# return. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r r,a8836,76543210 +#r I,0 +#r I,8 +#r r,a8830,eeff4455 +#r r,a8834,dd001122 +#r r,a8838,aaeeff44 +#r r,a883c,ff445511 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + moveq -1,$r4 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + + ei + test_h_mem 0,dummy + + ; Here after the first interrupt, or perhaps the second interrupt is + ; taken directly; leave it optional. Anyway, the second interrupt + ; should be taken no later than this branch. + test_h_mem 0,dummy + +killme: + fail + +irq0x33: + .if ..asm.arch.cris.v32 + ; Nothing needed to save flags - "shift" should happen, and back at rfe. + .else + ; The missing sim support for interrupt-excluding instructions is matched + ; by the flaw that sim doesn't service interrupts in straight code. + ; So, we can use a sequence that would work on actual hardware. + move $dccr,$r5 + di + .endif + + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + test_h_mem 0xdd001122 0xd0000034 + moveq -22,$r4 + + .if ..asm.arch.cris.v32 + move irqvec2,$ebp + rete + rfe + .else + move irqvec2,$ibr + reti + move $r5,$dccr + .endif + + pass + +irq0x34: + test_h_mem 0xaaeeff44 0xd0000038 + test_h_mem 0xff445511 0xd000003c + cmpq -22,$r4 + bne killme + nop + pass + + singlevec irqvec1,0x33,irq0x33 + + singlevec irqvec2,0x34,irq0x34 Index: cris/crisv32f.c =================================================================== RCS file: /cvs/src/src/sim/cris/crisv32f.c,v retrieving revision 1.2 diff -p -u -r1.2 crisv32f.c --- cris/crisv32f.c 3 Apr 2006 03:01:45 -0000 1.2 +++ cris/crisv32f.c 8 Apr 2006 17:27:49 -0000 @@ -590,6 +590,8 @@ MY (deliver_interrupt) (SIM_CPU *current recognize that we're in kernel mode. */ CPU (h_ubit_v32) = 0; + SET_H_SR (H_SR_CCS, new_ccs); + if (was_user) { /* These methods require that user mode is unset. */ brgds, H-P