From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28074 invoked by alias); 6 Dec 2005 22:46:49 -0000 Received: (qmail 28067 invoked by uid 22791); 6 Dec 2005 22:46:49 -0000 X-Spam-Check-By: sourceware.org Received: from miranda.se.axis.com (HELO miranda.se.axis.com) (193.13.178.8) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 06 Dec 2005 22:46:46 +0000 Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.83.5.18]) by miranda.se.axis.com (8.12.9/8.12.9/Debian-5local0.1) with ESMTP id jB6MkiWN011069; Tue, 6 Dec 2005 23:46:44 +0100 Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id jB6MkhmC017585; Tue, 6 Dec 2005 23:46:43 +0100 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id jB6MkhvQ017581; Tue, 6 Dec 2005 23:46:43 +0100 Date: Wed, 07 Dec 2005 15:18:00 -0000 Message-Id: <200512062246.jB6MkhvQ017581@ignucius.se.axis.com> From: Hans-Peter Nilsson To: gdb-patches@sourceware.org Subject: Committed: sim/cris: no writes to read-only special registers except specializations Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2005-12/txt/msg00124.txt.bz2 It started as a need to simulate a 32-bit branch expansion that doesn't affect condition codes. The expansion being "move [$pc=$pc+offs],$p0" and because of the insn encoding, it seemed best to handle as invalid writes to read-only special registers as there'd otherwise be a ambiguity between a [PC+] meaning (when prefixed) a PC assignment (i.e. jump) or (otherwise) a constant; field parsing is AFAIK static in CGEN sims and can't be affected by simulator state. The actual sim changes are to cris.cpu and sent to binutils@. Committed. sim/: * cris/cpuv10.h, cris/cpuv32.h, cris/cris-desc.c, cris/cris-opc.h, cris/decodev10.c, cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, cris/semcrisv32f-switch.c: Regenerate. sim/testsuite/: * sim/cris/asm/movmp8.ms, sim/cris/asm/pcplus.ms: New tests. * sim/cris/asm/movmp.ms: Do not write to P0, P4 or P8. * sim/cris/asm/raw13.ms: Write to MOF instead of WZ (P4). Index: sim/cris/asm/movmp.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/movmp.ms,v retrieving revision 1.1 diff -p -u -r1.1 movmp.ms --- sim/cris/asm/movmp.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/movmp.ms 6 Dec 2005 22:04:02 -0000 @@ -16,9 +16,14 @@ filler: .text ; Test that writing to zero-registers is a nop + .if 0 + ; We used to just ignore the writes, but now an error is emitted. We + ; keep the test-code but disabled, in case we need to change this again. move 0xaa,p0 move 0x4433,p4 move 0x55774433,p8 + .endif + moveq -1,r3 setf zcvn clear.b r3 @@ -36,10 +41,13 @@ filler: dumpr3 ; "Write" using ordinary memory references too. + .if 0 ; See ".if 0" above. move.d filler,r6 move [r6],p0 move [r6],p4 move [r6],p8 + .endif + moveq -1,r3 clear.b r3 dumpr3 @@ -53,9 +61,12 @@ filler: dumpr3 ; And postincremented. + .if 0 ; See ".if 0" above. move [r6+],p0 move [r6+],p4 move [r6+],p8 + .endif + moveq -1,r3 clear.b r3 dumpr3 Index: sim/cris/asm/movmp8.ms =================================================================== RCS file: sim/cris/asm/movmp8.ms diff -N sim/cris/asm/movmp8.ms --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/cris/asm/movmp8.ms 6 Dec 2005 22:04:02 -0000 @@ -0,0 +1,33 @@ +# mach: crisv3 crisv8 crisv10 + +# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux. + + .include "testutils.inc" + startnostack + move.d x,$sp + moveq 0,$r3 + move [$sp=$sp+16],$p8 + ; Z not changed. + bne 0f + nop + cmp.d x+16,$sp + bne 0f + nop + move $p8,$r3 + ; Z not changed. + bne 0f + ; P8 still 0. + test.d $r3 + bne 0f + nop + pass +0: + fail + + .data +x: + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff + .dword 0xffffffff Index: sim/cris/asm/pcplus.ms =================================================================== RCS file: sim/cris/asm/pcplus.ms diff -N sim/cris/asm/pcplus.ms --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/cris/asm/pcplus.ms 6 Dec 2005 22:04:02 -0000 @@ -0,0 +1,46 @@ +# mach: crisv0 crisv3 crisv8 crisv10 + +; Test that a forward as well as backward 32-bit "branch" expansion +; works including that the right offset is applied. + + .macro nop32 + .rept 32 + nop + .endr + .endm + + .include "testutils.inc" + start + jump start1 + fail + + nop32 + subq 63,$r10 +9: subq 1,$r10 + nop32 + jump 0f + + fail +0: move [$pc=$pc+1f-6-0b],$p0 + nop32 + fail + + .skip 32768,0 + + nop32 + subq 63,$r10 +1: + subq 1,$r10 + nop32 + test.d $r10 + bne 7f + nop + pass +7: + fail + +start1: + moveq 2,$r10 +0: move [$pc=$pc+9b-6-0b],$p0 + subq 63,$r10 + fail Index: sim/cris/asm/raw13.ms =================================================================== RCS file: /cvs/src/src/sim/testsuite/sim/cris/asm/raw13.ms,v retrieving revision 1.1 diff -p -u -r1.1 raw13.ms --- sim/cris/asm/raw13.ms 21 Nov 2005 04:48:19 -0000 1.1 +++ sim/cris/asm/raw13.ms 6 Dec 2005 22:04:02 -0000 @@ -1,4 +1,4 @@ -; Checking read-after-write: write-WZ-then-read unaffected. +; Checking read-after-write: write-MOF-then-read unaffected. #mach: crisv32 #output: Basic clock cycles, total @: 4\n #output: Memory source stall cycles: 0\n @@ -17,6 +17,6 @@ .lcomm y,4 move.d x,$r0 move.d y,$r1 - move [$r0],$wz + move [$r0],$mof move [$r1],$srp break 15 brgds, H-P