From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19195 invoked by alias); 25 Mar 2005 12:26:58 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 19058 invoked from network); 25 Mar 2005 12:26:49 -0000 Received: from unknown (HELO sibelius.xs4all.nl) (82.92.89.47) by sourceware.org with SMTP; 25 Mar 2005 12:26:49 -0000 Received: from elgar.sibelius.xs4all.nl (root@elgar.sibelius.xs4all.nl [192.168.0.2]) by sibelius.xs4all.nl (8.13.0/8.13.0) with ESMTP id j2PCQdFL003297; Fri, 25 Mar 2005 13:26:39 +0100 (CET) Received: from elgar.sibelius.xs4all.nl (kettenis@localhost.sibelius.xs4all.nl [127.0.0.1]) by elgar.sibelius.xs4all.nl (8.13.3/8.13.3) with ESMTP id j2PCQdHt019643; Fri, 25 Mar 2005 13:26:39 +0100 (CET) Received: (from kettenis@localhost) by elgar.sibelius.xs4all.nl (8.13.3/8.13.3/Submit) id j2PCQZMf031903; Fri, 25 Mar 2005 13:26:35 +0100 (CET) Date: Fri, 25 Mar 2005 12:26:00 -0000 Message-Id: <200503251226.j2PCQZMf031903@elgar.sibelius.xs4all.nl> From: Mark Kettenis To: brobecker@adacore.com CC: gdb-patches@sources.redhat.com In-reply-to: <20050325054917.GC32590@adacore.com> (message from Joel Brobecker on Thu, 24 Mar 2005 21:49:17 -0800) Subject: Re: [RFC/mips] Problem with fetching/setting 32 bit registers References: <20050324041407.GG1324@adacore.com> <20050324042630.GA1262@nevyn.them.org> <20050325054917.GC32590@adacore.com> X-SW-Source: 2005-03/txt/msg00310.txt.bz2 Date: Thu, 24 Mar 2005 21:49:17 -0800 From: Joel Brobecker Daniel, > This appears to be a bug in your native support, at least relative to > the rest of the MIPS port. Thanks to your help, I think I actually better what happens, now. It's a size issue: fpregsetp->fp_csr is 32bits long, while the value stored int the raw part of the regcache is 64 bits. So when we do the memcpy inside regcache_raw_supply(), we end up copying the FSR register value at the first 4 bytes of the regcache buffer, and then some other junk. When comes the time to transform this raw register into a cooked register, we naturally look at the last 4 bytes... I am currently testing the attached patch. Doesn't it look better? Looks better but: Index: irix5-nat.c =================================================================== RCS file: /gnat.dev/cvs/Dev/gdb/gdb-6.3/gdb/irix5-nat.c,v retrieving revision 1.2 diff -u -p -r1.2 irix5-nat.c --- irix5-nat.c 18 Nov 2004 10:49:32 -0000 1.2 +++ irix5-nat.c 25 Mar 2005 05:46:56 -0000 @@ -157,6 +157,7 @@ supply_fpregset (fpregset_t *fpregsetp) { int regi; static char zerobuf[32] = {0}; + char fsrbuf[64]; Looks like you're confused about bits and bytes. Guess 8 is large enough here ;-). /* FIXME, this is wrong for the N32 ABI which has 64 bit FP regs. */ Could you remove the redundant parenthesis here while you're at it: @@ -194,7 +203,20 @@ fill_fpregset (fpregset_t *fpregsetp, in if ((regno == -1) || (regno == mips_regnum (current_gdbarch)->fp_control_status)) - fpregsetp->fp_csr = *(unsigned *) &deprecated_registers[DEPRECATED_REGISTER_BYTE (mips_regnum (current_gdbarch)->fp_control_status)]; + { + char fsrbuf[64]; + + /* We can't fill the FSR register directly from the regcache, + because there is a size issue: On one hand, fpregsetp->fp_csr + is 32bits long, while the regcache expects a 64bits long buffer. + So we use a buffer of the correct size and copy the register + value from that buffer. */ + regcache_raw_read (current_regcache, + mips_regnum (current_gdbarch)->fp_control_status, + fsrbuf); + + memcpy (&fpregsetp->fp_csr, fsrbuf + 4, 4); + } }