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From: Joel Brobecker <brobecker@adacore.com>
To: gdb-patches@sources.redhat.com
Subject: Re: [RFC/mips] Problem with fetching/setting 32 bit registers
Date: Fri, 25 Mar 2005 05:49:00 -0000	[thread overview]
Message-ID: <20050325054917.GC32590@adacore.com> (raw)
In-Reply-To: <20050324042630.GA1262@nevyn.them.org>

Daniel,

> This appears to be a bug in your native support, at least relative to
> the rest of the MIPS port.

Thanks to your help, I think I actually better what happens, now. It's a
size issue: fpregsetp->fp_csr is 32bits long, while the value stored int
the raw part of the regcache is 64 bits. So when we do the memcpy inside
regcache_raw_supply(), we end up copying the FSR register value at the
first 4 bytes of the regcache buffer, and then some other junk. When
comes the time to transform this raw register into a cooked register, we
naturally look at the last 4 bytes...

I am currently testing the attached patch. Doesn't it look better?

Thanks,
-- 
Joel


Index: irix5-nat.c
===================================================================
RCS file: /gnat.dev/cvs/Dev/gdb/gdb-6.3/gdb/irix5-nat.c,v
retrieving revision 1.2
diff -u -p -r1.2 irix5-nat.c
--- irix5-nat.c	18 Nov 2004 10:49:32 -0000	1.2
+++ irix5-nat.c	25 Mar 2005 05:46:56 -0000
@@ -157,6 +157,7 @@ supply_fpregset (fpregset_t *fpregsetp)
 {
   int regi;
   static char zerobuf[32] = {0};
+  char fsrbuf[64];
 
   /* FIXME, this is wrong for the N32 ABI which has 64 bit FP regs. */
 
@@ -164,9 +165,17 @@ supply_fpregset (fpregset_t *fpregsetp)
     regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
 			 (char *) &fpregsetp->fp_r.fp_regs[regi]);
 
+  /* We can't supply the FSR register directly to the regcache,
+     because there is a size issue: On one hand, fpregsetp->fp_csr
+     is 32bits long, while the regcache expects a 64bits long value.
+     So we use a buffer of the correct size and copy into it the register
+     value at the proper location.  */
+  memset (fsrbuf, 0, 4);
+  memcpy (fsrbuf + 4, &fpregsetp->fp_csr, 4);
+
   regcache_raw_supply (current_regcache,
 		       mips_regnum (current_gdbarch)->fp_control_status,
-		       (char *) &fpregsetp->fp_csr);
+		       fsrbuf);
 
   /* FIXME: how can we supply FCRIR?  SGI doesn't tell us. */
   regcache_raw_supply (current_regcache,
@@ -194,7 +203,20 @@ fill_fpregset (fpregset_t *fpregsetp, in
 
   if ((regno == -1)
       || (regno == mips_regnum (current_gdbarch)->fp_control_status))
-    fpregsetp->fp_csr = *(unsigned *) &deprecated_registers[DEPRECATED_REGISTER_BYTE (mips_regnum (current_gdbarch)->fp_control_status)];
+    {
+      char fsrbuf[64];
+
+    /* We can't fill the FSR register directly from the regcache,
+       because there is a size issue: On one hand, fpregsetp->fp_csr
+       is 32bits long, while the regcache expects a 64bits long buffer.
+       So we use a buffer of the correct size and copy the register
+       value from that buffer.  */
+      regcache_raw_read (current_regcache,
+                         mips_regnum (current_gdbarch)->fp_control_status,
+                         fsrbuf);
+
+      memcpy (&fpregsetp->fp_csr, fsrbuf + 4, 4);
+    }
 }
 
 


  reply	other threads:[~2005-03-25  5:49 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-03-24  4:14 Joel Brobecker
2005-03-24  4:26 ` Daniel Jacobowitz
2005-03-25  5:49   ` Joel Brobecker [this message]
2005-03-25 12:26     ` Mark Kettenis
2005-03-26  0:39       ` Joel Brobecker

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