From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26362 invoked by alias); 23 Feb 2004 21:39:04 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 26321 invoked from network); 23 Feb 2004 21:38:58 -0000 Received: from unknown (HELO walton.kettenis.dyndns.org) (213.93.115.144) by sources.redhat.com with SMTP; 23 Feb 2004 21:38:58 -0000 Received: from elgar.kettenis.dyndns.org (elgar.kettenis.dyndns.org [192.168.0.2]) by walton.kettenis.dyndns.org (8.12.6p3/8.12.6) with ESMTP id i1NLcvKb000337 for ; Mon, 23 Feb 2004 22:38:57 +0100 (CET) (envelope-from kettenis@elgar.kettenis.dyndns.org) Received: from elgar.kettenis.dyndns.org (localhost [127.0.0.1]) by elgar.kettenis.dyndns.org (8.12.6p3/8.12.6) with ESMTP id i1NLcvYB000423 for ; Mon, 23 Feb 2004 22:38:57 +0100 (CET) (envelope-from kettenis@elgar.kettenis.dyndns.org) Received: (from kettenis@localhost) by elgar.kettenis.dyndns.org (8.12.6p3/8.12.6/Submit) id i1NLcvWW000420; Mon, 23 Feb 2004 22:38:57 +0100 (CET) Date: Mon, 23 Feb 2004 21:39:00 -0000 Message-Id: <200402232138.i1NLcvWW000420@elgar.kettenis.dyndns.org> From: Mark Kettenis To: gdb-patches@sources.redhat.com Subject: [PATCH] Final s/x86_64/amd64g X-SW-Source: 2004-02/txt/msg00663.txt.bz2 Even though Intel won't like it ;-). Committed. All that remains to be done now is renaming a few files. Mark. Index: ChangeLog from Mark Kettenis * x86-64-tdep.h: Tewak comment. (enum amd64_regnum): New. (X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, X86_64_RDI_REGNUM) (X86_64_RBP_REGNUM, X86_64_RSP_REGNUM, X86_64_RIP_REGNUM) (X86_64_EFLAGS_REGNUM, X86_64_ST0_REGNUM, X86_64_XMM0_REGNUM) (X86_64_XMM1_REGNUM): Removed. (AMD64_NUM_GREGS): Renamed from X86_64_NUM_GREGS. (amd64_init_abi, amd64_supply_fxsave, amd64_fill_fxsave): Adjust prototypes for renamed functions. * x86-64-tdep.c: Fix typo. (amd64_dwarf_regmap): Use constants from `enum amd64_regnum' for register numbers. (amd64_return_value, amd64_push_arguments, amd64_push_dummy_call): Use constants from `enum amd64_regnum' for register numbers. (AMD64_NUM_SAVED_REGS): Adjust for renamed macros. (amd64_analyze_prologue, amd64_frame_cache, amd64_sigtramp_frame_cache): Use constants from `enum amd64_regnum' for register numbers. (amd64_supply_fpregset): Adjust for renamed functions. (amd64_init_abi): Rename from x86_64_init_abi. Use constants from `enum amd64_regnum' for register numbers. (I387_ST0_REGNUM): Use constant from `enum amd64_regnum'. (amd64_supply_fxsave): Rename from x86_64_supply_fxsave. (amd64_fill_fxsave): Rename fro x86_64_fill_fxsave. * x86-64-linux-tdep.c (amd64_linux_supply_gregset) (amd64_linux_fill_gregset): Adjust for renamed macros. (fetch_core_registers): Adjust for renamed functions. (amd64_linux_init_abi): Adjust for renamed functions. * x86-64-linux-nat.c (supply_gregset, fill_gregset): Adjust for renamed functions. * amd64-nat.c: Adjust for renamed macros. * amd64bsd-nat.c (fetch_inferior_registers) (store_inferior_registers): Use constants from `enum amd64_regnum' for register numbers. Adjust for renamed variables. * amd64fbsd-nat.c (supply_gregset, fill_gregset): Adjust for renamed variables. (_initialize_amd64fbsd_nat): Use constants from `enum amd64_regnum' for register numbers. * amd64fbsd-tdep.c (amd64fbsd_sigcontext_addr): Use constants from `enum amd64_regnum' for register numbers. (amd64fbsd_init_abi): Adjust for renamed functions. * amd64nbsd-tdep.c (amd64nbsd_sigcontext_addr): Use constants from `enum amd64_regnum' for register numbers. (amd64nbsd_init_abi): Adjust for renamed functions. (_initialize_amd64nbsd_ndep): Adjust for renamed macros. * amd64obsd-tdep.c (amd64obsd_sigcontext_addr): Use constants from `enum amd64_regnum' for register numbers. (amd64obsd_init_abi): Adjust for renamed functions. (_initialize_amd64obsd_ndep): Adjust for renamed macros. Index: x86-64-linux-nat.c =================================================================== RCS file: /cvs/src/src/gdb/x86-64-linux-nat.c,v retrieving revision 1.33 diff -u -p -r1.33 x86-64-linux-nat.c --- x86-64-linux-nat.c 22 Feb 2004 20:19:40 -0000 1.33 +++ x86-64-linux-nat.c 23 Feb 2004 21:18:30 -0000 @@ -166,7 +166,7 @@ store_regs (int tid, int regnum) void supply_fpregset (elf_fpregset_t *fpregsetp) { - x86_64_supply_fxsave (current_regcache, -1, fpregsetp); + amd64_supply_fxsave (current_regcache, -1, fpregsetp); } /* Fill register REGNUM (if it is a floating-point or SSE register) in @@ -176,7 +176,7 @@ supply_fpregset (elf_fpregset_t *fpregse void fill_fpregset (elf_fpregset_t *fpregsetp, int regnum) { - x86_64_fill_fxsave ((char *) fpregsetp, regnum); + amd64_fill_fxsave ((char *) fpregsetp, regnum); } /* Fetch all floating-point registers from process/thread TID and store Index: x86-64-linux-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/x86-64-linux-tdep.c,v retrieving revision 1.26 diff -u -p -r1.26 x86-64-linux-tdep.c --- x86-64-linux-tdep.c 22 Feb 2004 20:29:48 -0000 1.26 +++ x86-64-linux-tdep.c 23 Feb 2004 21:18:30 -0000 @@ -80,7 +80,7 @@ amd64_linux_supply_gregset (char *regp) { int i; - for (i = 0; i < X86_64_NUM_GREGS; i++) + for (i = 0; i < AMD64_NUM_GREGS; i++) supply_register (i, regp + (user_to_gdb_regmap[i] * 8)); } @@ -93,7 +93,7 @@ amd64_linux_fill_gregset (char *regp, in { int i; - for (i = 0; i < X86_64_NUM_GREGS; i++) + for (i = 0; i < AMD64_NUM_GREGS; i++) if (regno == -1 || regno == i) regcache_collect (i, regp + (user_to_gdb_regmap[i] * 8)); } @@ -123,7 +123,7 @@ fetch_core_registers (char *core_reg_sec if (core_reg_size != 512) warning ("Wrong size XMM register set in core file."); else - x86_64_supply_fxsave (current_regcache, -1, core_reg_sect); + amd64_supply_fxsave (current_regcache, -1, core_reg_sect); break; default: @@ -271,7 +271,7 @@ static void amd64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - x86_64_init_abi (info, gdbarch); + amd64_init_abi (info, gdbarch); set_gdbarch_pc_in_sigtramp (gdbarch, amd64_linux_pc_in_sigtramp); Index: x86-64-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/x86-64-tdep.c,v retrieving revision 1.112 diff -u -p -r1.112 x86-64-tdep.c --- x86-64-tdep.c 17 Jan 2004 22:45:44 -0000 1.112 +++ x86-64-tdep.c 23 Feb 2004 21:18:31 -0000 @@ -42,7 +42,7 @@ /* Note that the AMD64 architecture was previously known as x86-64. The latter is (forever) engraved into the canonical system name as - returned bu config.guess, and used as the name for the AMD64 port + returned by config.guess, and used as the name for the AMD64 port of GNU/Linux. The BSD's have renamed their ports to amd64; they don't like to shout. For GDB we prefer the amd64_-prefix over the x86_64_-prefix since it's so much easier to type. */ @@ -154,38 +154,39 @@ amd64_register_type (struct gdbarch *gdb static int amd64_dwarf_regmap[] = { /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ - X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1, - 4, X86_64_RDI_REGNUM, + AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, + AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, + AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, /* Frame Pointer Register RBP. */ - X86_64_RBP_REGNUM, + AMD64_RBP_REGNUM, /* Stack Pointer Register RSP. */ - X86_64_RSP_REGNUM, + AMD64_RSP_REGNUM, /* Extended Integer Registers 8 - 15. */ 8, 9, 10, 11, 12, 13, 14, 15, /* Return Address RA. Mapped to RIP. */ - X86_64_RIP_REGNUM, + AMD64_RIP_REGNUM, /* SSE Registers 0 - 7. */ - X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM, - X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3, - X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5, - X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7, + AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, + AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, + AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, + AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, /* Extended SSE Registers 8 - 15. */ - X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9, - X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11, - X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13, - X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15, + AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, + AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, + AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, + AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, /* Floating Point Registers 0-7. */ - X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1, - X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3, - X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5, - X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7 + AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, + AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, + AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, + AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7 }; static const int amd64_dwarf_regmap_len = @@ -406,8 +407,8 @@ amd64_return_value (struct gdbarch *gdba { enum amd64_reg_class class[2]; int len = TYPE_LENGTH (type); - static int integer_regnum[] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM }; - static int sse_regnum[] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM }; + static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; + static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; int integer_reg = 0; int sse_reg = 0; int i; @@ -457,7 +458,7 @@ amd64_return_value (struct gdbarch *gdba case AMD64_X87: /* 6. If the class is X87, the value is returned on the X87 stack in %st0 as 80-bit x87 number. */ - regnum = X86_64_ST0_REGNUM; + regnum = AMD64_ST0_REGNUM; if (writebuf) i387_return_value (gdbarch, regcache); break; @@ -466,7 +467,7 @@ amd64_return_value (struct gdbarch *gdba /* 7. If the class is X87UP, the value is returned together with the previous X87 value in %st0. */ gdb_assert (i > 0 && class[0] == AMD64_X87); - regnum = X86_64_ST0_REGNUM; + regnum = AMD64_ST0_REGNUM; offset = 8; len = 2; break; @@ -498,17 +499,20 @@ amd64_push_arguments (struct regcache *r { static int integer_regnum[] = { - X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */ - X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */ - 8, 9 /* %r8, %r9 */ + AMD64_RDI_REGNUM, /* %rdi */ + AMD64_RSI_REGNUM, /* %rsi */ + AMD64_RDX_REGNUM, /* %rdx */ + AMD64_RCX_REGNUM, /* %rcx */ + 8, /* %r8 */ + 9 /* %r9 */ }; static int sse_regnum[] = { /* %xmm0 ... %xmm7 */ - X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM, - X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3, - X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5, - X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7, + AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, + AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, + AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, + AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, }; struct value **stack_args = alloca (nargs * sizeof (struct value *)); int num_stack_args = 0; @@ -617,7 +621,7 @@ amd64_push_arguments (struct regcache *r varargs or stdargs (prototype-less calls or calls to functions containing ellipsis (...) in the declaration) %al is used as hidden argument to specify the number of SSE registers used. */ - regcache_raw_write_unsigned (regcache, X86_64_RAX_REGNUM, sse_reg); + regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); return sp; } @@ -636,7 +640,7 @@ amd64_push_dummy_call (struct gdbarch *g if (struct_return) { store_unsigned_integer (buf, 8, struct_addr); - regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf); + regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); } /* Store return address. */ @@ -646,17 +650,17 @@ amd64_push_dummy_call (struct gdbarch *g /* Finally, update the stack pointer... */ store_unsigned_integer (buf, 8, sp); - regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf); + regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); /* ...and fake a frame pointer. */ - regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf); + regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); return sp + 16; } /* The maximum number of saved registers. This should include %rip. */ -#define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS +#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS struct amd64_frame_cache { @@ -729,7 +733,7 @@ amd64_analyze_prologue (CORE_ADDR pc, CO { /* Take into account that we've executed the `pushq %rbp' that starts this instruction sequence. */ - cache->saved_regs[X86_64_RBP_REGNUM] = 0; + cache->saved_regs[AMD64_RBP_REGNUM] = 0; cache->sp_offset += 8; /* If that's all, return now. */ @@ -794,12 +798,12 @@ amd64_frame_cache (struct frame_info *ne frame by looking at the stack pointer. For truly "frameless" functions this might work too. */ - frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf); + frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; } else { - frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf); + frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); cache->base = extract_unsigned_integer (buf, 8); } @@ -810,7 +814,7 @@ amd64_frame_cache (struct frame_info *ne /* For normal frames, %rip is stored at 8(%rbp). If we don't have a frame we find it at the same offset from the reconstructed base address. */ - cache->saved_regs[X86_64_RIP_REGNUM] = 8; + cache->saved_regs[AMD64_RIP_REGNUM] = 8; /* Adjust all the saved registers such that they contain addresses instead of offsets. */ @@ -913,7 +917,7 @@ amd64_sigtramp_frame_cache (struct frame cache = amd64_alloc_frame_cache (); - frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf); + frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); cache->base = extract_unsigned_integer (buf, 8) - 8; addr = tdep->sigcontext_addr (next_frame); @@ -999,7 +1003,7 @@ amd64_unwind_dummy_id (struct gdbarch *g char buf[8]; CORE_ADDR fp; - frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf); + frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); fp = extract_unsigned_integer (buf, 8); return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); @@ -1025,7 +1029,7 @@ amd64_supply_fpregset (const struct regs const struct gdbarch_tdep *tdep = regset->descr; gdb_assert (len == tdep->sizeof_fpregset); - x86_64_supply_fxsave (regcache, regnum, fpregs); + amd64_supply_fxsave (regcache, regnum, fpregs); } /* Return the appropriate register set for the core section identified @@ -1054,7 +1058,7 @@ amd64_regset_from_core_section (struct g void -x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -1063,7 +1067,7 @@ x86_64_init_abi (struct gdbarch_info inf tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; /* AMD64 has an FPU and 16 SSE registers. */ - tdep->st0_regnum = X86_64_ST0_REGNUM; + tdep->st0_regnum = AMD64_ST0_REGNUM; tdep->num_xmm_regs = 16; /* This is what all the fuss is about. */ @@ -1081,10 +1085,10 @@ x86_64_init_abi (struct gdbarch_info inf set_gdbarch_register_type (gdbarch, amd64_register_type); /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */ - set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */ - set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */ - set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */ + set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ + set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ + set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ + set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ /* The "default" register numbering scheme for AMD64 is referred to as the "DWARF Register Number Mapping" in the System V psABI. @@ -1134,7 +1138,7 @@ x86_64_init_abi (struct gdbarch_info inf } -#define I387_ST0_REGNUM X86_64_ST0_REGNUM +#define I387_ST0_REGNUM AMD64_ST0_REGNUM /* The 64-bit FXSAVE format differs from the 32-bit format in the sense that the instruction pointer and data pointer are simply @@ -1149,7 +1153,7 @@ x86_64_init_abi (struct gdbarch_info inf reserved bits in *FXSAVE. */ void -x86_64_supply_fxsave (struct regcache *regcache, int regnum, +amd64_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { i387_supply_fxsave (regcache, regnum, fxsave); @@ -1171,7 +1175,7 @@ x86_64_supply_fxsave (struct regcache *r reserved bits in *FXSAVE. */ void -x86_64_fill_fxsave (char *fxsave, int regnum) +amd64_fill_fxsave (char *fxsave, int regnum) { i387_fill_fxsave (fxsave, regnum); Index: x86-64-tdep.h =================================================================== RCS file: /cvs/src/src/gdb/x86-64-tdep.h,v retrieving revision 1.24 diff -u -p -r1.24 x86-64-tdep.h --- x86-64-tdep.h 22 Feb 2004 19:14:55 -0000 1.24 +++ x86-64-tdep.h 23 Feb 2004 21:18:31 -0000 @@ -1,4 +1,4 @@ -/* Target-dependent code for the x86-64. +/* Target-dependent definitions for AMD64. Copyright 2001, 2003, 2004 Free Software Foundation, Inc. Contributed by Jiri Smid, SuSE Labs. @@ -31,36 +31,44 @@ struct regcache; /* Register numbers of various important registers. */ -#define X86_64_RAX_REGNUM 0 /* %rax */ -#define X86_64_RDX_REGNUM 3 /* %rdx */ -#define X86_64_RDI_REGNUM 5 /* %rdi */ -#define X86_64_RBP_REGNUM 6 /* %rbp */ -#define X86_64_RSP_REGNUM 7 /* %rsp */ -#define X86_64_RIP_REGNUM 16 /* %rip */ -#define X86_64_EFLAGS_REGNUM 17 /* %eflags */ -#define X86_64_ST0_REGNUM 24 /* %st0 */ -#define X86_64_XMM0_REGNUM 40 /* %xmm0 */ -#define X86_64_XMM1_REGNUM 41 /* %xmm1 */ +enum amd64_regnum +{ + AMD64_RAX_REGNUM, /* %rax */ + AMD64_RBX_REGNUM, /* %rbx */ + AMD64_RCX_REGNUM, /* %rcx */ + AMD64_RDX_REGNUM, /* %rdx */ + AMD64_RSI_REGNUM, /* %rsi */ + AMD64_RDI_REGNUM, /* %rdi */ + AMD64_RBP_REGNUM, /* %rbp */ + AMD64_RSP_REGNUM, /* %rsp */ + AMD64_R8_REGNUM = 8, /* %r8 */ + AMD64_R15_REGNUM = 15, /* %r15 */ + AMD64_RIP_REGNUM, /* %rip */ + AMD64_EFLAGS_REGNUM, /* %eflags */ + AMD64_ST0_REGNUM = 24, /* %st0 */ + AMD64_XMM0_REGNUM = 40, /* %xmm0 */ + AMD64_XMM1_REGNUM /* %xmm1 */ +}; /* Number of general purpose registers. */ -#define X86_64_NUM_GREGS 24 +#define AMD64_NUM_GREGS 24 -void x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch); +extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch); /* Fill register REGNUM in REGCACHE with the appropriate floating-point or SSE register value from *FXSAVE. If REGNUM is -1, do this for all registers. This function masks off any of the reserved bits in *FXSAVE. */ -extern void x86_64_supply_fxsave (struct regcache *regcache, int regnum, - const void *fxsave); +extern void amd64_supply_fxsave (struct regcache *regcache, int regnum, + const void *fxsave); /* Fill register REGNUM (if it is a floating-point or SSE register) in *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do this for all registers. This function doesn't touch any of the reserved bits in *FXSAVE. */ -void x86_64_fill_fxsave (char *fxsave, int regnum); +extern void amd64_fill_fxsave (char *fxsave, int regnum); /* Variables exported from amd64nbsd-tdep.c. */ Index: amd64-nat.c =================================================================== RCS file: /cvs/src/src/gdb/amd64-nat.c,v retrieving revision 1.2 diff -u -p -r1.2 amd64-nat.c --- amd64-nat.c 21 Feb 2004 23:50:40 -0000 1.2 +++ amd64-nat.c 23 Feb 2004 21:18:32 -0000 @@ -46,7 +46,7 @@ int amd64_native_gregset32_num_regs = I3 /* General-purpose register mapping for native 64-bit code. */ int *amd64_native_gregset64_reg_offset; -int amd64_native_gregset64_num_regs = X86_64_NUM_GREGS; +int amd64_native_gregset64_num_regs = AMD64_NUM_GREGS; /* Return the offset of REGNUM within the appropriate native general-purpose register set. */ Index: amd64bsd-nat.c =================================================================== RCS file: /cvs/src/src/gdb/amd64bsd-nat.c,v retrieving revision 1.1 diff -u -p -r1.1 amd64bsd-nat.c --- amd64bsd-nat.c 18 Oct 2003 18:41:22 -0000 1.1 +++ amd64bsd-nat.c 23 Feb 2004 21:18:32 -0000 @@ -54,7 +54,7 @@ fetch_inferior_registers (int regnum) return; } - if (regnum == -1 || regnum >= X86_64_ST0_REGNUM) + if (regnum == -1 || regnum >= AMD64_ST0_REGNUM) { struct fpreg fpregs; @@ -62,7 +62,7 @@ fetch_inferior_registers (int regnum) (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) perror_with_name ("Couldn't get floating point status"); - x86_64_supply_fxsave (current_regcache, -1, &fpregs); + amd64_supply_fxsave (current_regcache, -1, &fpregs); } } @@ -90,7 +90,7 @@ store_inferior_registers (int regnum) return; } - if (regnum == -1 || regnum >= X86_64_ST0_REGNUM) + if (regnum == -1 || regnum >= AMD64_ST0_REGNUM) { struct fpreg fpregs; @@ -98,7 +98,7 @@ store_inferior_registers (int regnum) (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) perror_with_name ("Couldn't get floating point status"); - x86_64_fill_fxsave ((char *) &fpregs, regnum); + amd64_fill_fxsave ((char *) &fpregs, regnum); if (ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) Index: amd64fbsd-nat.c =================================================================== RCS file: /cvs/src/src/gdb/amd64fbsd-nat.c,v retrieving revision 1.10 diff -u -p -r1.10 amd64fbsd-nat.c --- amd64fbsd-nat.c 22 Feb 2004 19:14:55 -0000 1.10 +++ amd64fbsd-nat.c 23 Feb 2004 21:18:32 -0000 @@ -131,7 +131,7 @@ fill_gregset (gregset_t *gregsetp, int r void supply_fpregset (fpregset_t *fpregsetp) { - x86_64_supply_fxsave (current_regcache, -1, fpregsetp); + amd64_supply_fxsave (current_regcache, -1, fpregsetp); } /* Fill register REGNUM (if it is a floating-point register) in @@ -141,7 +141,7 @@ supply_fpregset (fpregset_t *fpregsetp) void fill_fpregset (fpregset_t *fpregsetp, int regnum) { - x86_64_fill_fxsave ((char *) fpregsetp, regnum); + amd64_fill_fxsave ((char *) fpregsetp, regnum); } @@ -168,9 +168,9 @@ _initialize_amd64fbsd_nat (void) pointer since these members of `struct sigcontext' are essential for providing backtraces. */ -#define SC_RIP_OFFSET SC_REG_OFFSET[X86_64_RIP_REGNUM] -#define SC_RSP_OFFSET SC_REG_OFFSET[X86_64_RSP_REGNUM] -#define SC_RBP_OFFSET SC_REG_OFFSET[X86_64_RBP_REGNUM] +#define SC_RIP_OFFSET SC_REG_OFFSET[AMD64_RIP_REGNUM] +#define SC_RSP_OFFSET SC_REG_OFFSET[AMD64_RSP_REGNUM] +#define SC_RBP_OFFSET SC_REG_OFFSET[AMD64_RBP_REGNUM] /* Override the default value for the offset of the program counter in the sigcontext structure. */ Index: amd64fbsd-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/amd64fbsd-tdep.c,v retrieving revision 1.7 diff -u -p -r1.7 amd64fbsd-tdep.c --- amd64fbsd-tdep.c 22 Feb 2004 19:14:55 -0000 1.7 +++ amd64fbsd-tdep.c 23 Feb 2004 21:18:32 -0000 @@ -44,7 +44,7 @@ amd64fbsd_sigcontext_addr (struct frame_ /* The `struct sigcontext' (which really is an `ucontext_t' on FreeBSD/amd64) lives at a fixed offset in the signal frame. See . */ - sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM); + sp = frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM); return sp + 16; } @@ -130,7 +130,7 @@ amd64fbsd_init_abi (struct gdbarch_info tdep->gregset_num_regs = ARRAY_SIZE (amd64fbsd_r_reg_offset); tdep->sizeof_gregset = 22 * 8; - x86_64_init_abi (info, gdbarch); + amd64_init_abi (info, gdbarch); tdep->sigtramp_start = amd64fbsd_sigtramp_start_addr; tdep->sigtramp_end = amd64fbsd_sigtramp_end_addr; Index: amd64nbsd-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/amd64nbsd-tdep.c,v retrieving revision 1.3 diff -u -p -r1.3 amd64nbsd-tdep.c --- amd64nbsd-tdep.c 22 Feb 2004 16:20:22 -0000 1.3 +++ amd64nbsd-tdep.c 23 Feb 2004 21:18:32 -0000 @@ -43,7 +43,7 @@ amd64nbsd_sigcontext_addr (struct frame_ /* The stack pointer points at `struct sigcontext' upon entry of a signal trampoline. */ - sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM); + sp = frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM); return sp; } @@ -93,7 +93,7 @@ amd64nbsd_init_abi (struct gdbarch_info tdep->gregset_num_regs = ARRAY_SIZE (amd64nbsd_r_reg_offset); tdep->sizeof_gregset = 26 * 8; - x86_64_init_abi (info, gdbarch); + amd64_init_abi (info, gdbarch); tdep->jb_pc_offset = 7 * 8; @@ -128,7 +128,7 @@ void _initialize_amd64nbsd_ndep (void) { /* The NetBSD/amd64 native dependent code makes this assumption. */ - gdb_assert (ARRAY_SIZE (amd64nbsd_r_reg_offset) == X86_64_NUM_GREGS); + gdb_assert (ARRAY_SIZE (amd64nbsd_r_reg_offset) == AMD64_NUM_GREGS); gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NETBSD_ELF, amd64nbsd_init_abi); Index: amd64obsd-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/amd64obsd-tdep.c,v retrieving revision 1.4 diff -u -p -r1.4 amd64obsd-tdep.c --- amd64obsd-tdep.c 22 Feb 2004 16:20:22 -0000 1.4 +++ amd64obsd-tdep.c 23 Feb 2004 21:18:32 -0000 @@ -45,7 +45,7 @@ amd64obsd_supply_regset (const struct re gdb_assert (len >= tdep->sizeof_gregset + I387_SIZEOF_FXSAVE); i386_supply_gregset (regset, regcache, regnum, regs, tdep->sizeof_gregset); - x86_64_supply_fxsave (regcache, regnum, (char *)regs + tdep->sizeof_gregset); + amd64_supply_fxsave (regcache, regnum, (char *)regs + tdep->sizeof_gregset); } static const struct regset * @@ -112,7 +112,7 @@ amd64obsd_sigcontext_addr (struct frame_ { /* The %rsp register points at `struct sigcontext' upon entry of a signal trampoline. */ - return frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM); + return frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM); } /* OpenBSD 3.5 or later. */ @@ -183,7 +183,7 @@ amd64obsd_init_abi (struct gdbarch_info { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - x86_64_init_abi (info, gdbarch); + amd64_init_abi (info, gdbarch); /* Initialize general-purpose register set details. */ tdep->gregset_reg_offset = amd64obsd_r_reg_offset; @@ -213,7 +213,7 @@ void _initialize_amd64obsd_tdep (void) { /* The OpenBSD/amd64 native dependent code makes this assumption. */ - gdb_assert (ARRAY_SIZE (amd64obsd_r_reg_offset) == X86_64_NUM_GREGS); + gdb_assert (ARRAY_SIZE (amd64obsd_r_reg_offset) == AMD64_NUM_GREGS); gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_OPENBSD_ELF, amd64obsd_init_abi);