Re: Incorrect DWARF-2 register numbers on PPC64?

[Mark Kettenis <kettenis@chello.nl>]

   Date: Wed, 7 Jan 2004 01:57:10 +1030
   From: Alan Modra <amodra@bigpond.net.au>

   This patch corrects DWARF debug info register numbering for PPC targets.
   See http://gcc.gnu.org/ml/gcc/2004-01/msg00025.html for some background.

   I've also made a small fix to DWARF_REG_TO_UNWIND_COLUMN which
   incorrectly hardcoded an unwinder array index, and removed the confused
   FIXME.  See the new comment.

	   * config/rs6000/rs6000.c (rs6000_dbx_register_number): New function.
	   * config/rs6000/rs6000-protos.h (rs6000_dbx_register_number): Declare.
	   * config/rs6000/rs6000.h (DWARF_FRAME_REGNUM): Define.
	   (DWARF_REG_TO_UNWIND_COLUMN): Correct column adjustment and comment.
	   * config/rs6000/sysv4.h (DBX_REGISTER_NUMBER): Define.

   Bootstrapped powerpc-linux, no regressions.

   Index: gcc/config/rs6000/rs6000-protos.h
   ===================================================================
   RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000-protos.h,v
   retrieving revision 1.68
   diff -u -p -r1.68 rs6000-protos.h
   --- gcc/config/rs6000/rs6000-protos.h	9 Dec 2003 01:57:45 -0000	1.68
   +++ gcc/config/rs6000/rs6000-protos.h	6 Jan 2004 14:41:35 -0000
   @@ -186,6 +186,7 @@ extern int uses_TOC (void);
    extern void rs6000_emit_prologue (void);
    extern void rs6000_emit_load_toc_table (int);
    extern void rs6000_aix_emit_builtin_unwind_init (void);
   +extern unsigned int rs6000_dbx_register_number (unsigned int);
    extern void rs6000_emit_epilogue (int);
    extern void rs6000_emit_eh_reg_restore (rtx, rtx);
    extern const char * output_isel (rtx *);
   Index: gcc/config/rs6000/rs6000.c
   ===================================================================
   RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
   retrieving revision 1.565
   diff -u -p -r1.565 rs6000.c
   --- gcc/config/rs6000/rs6000.c	31 Dec 2003 00:25:51 -0000	1.565
   +++ gcc/config/rs6000/rs6000.c	6 Jan 2004 14:41:41 -0000
   @@ -15763,4 +15763,39 @@ rs6000_dwarf_register_span (rtx reg)
				      gen_rtx_REG (SImode, regno + 1200)));
    }

   +/* Map internal gcc register numbers to DWARF2 register numbers.  */
   +
   +unsigned int
   +rs6000_dbx_register_number (unsigned int regno)
   +{
   +  if (regno <= 63 || write_symbols != DWARF2_DEBUG)
   +    return regno;
   +  if (regno == MQ_REGNO)
   +    return 100;
   +  if (regno == LINK_REGISTER_REGNUM)
   +    return 108;
   +  if (regno == COUNT_REGISTER_REGNUM)
   +    return 109;
   +  if (CR_REGNO_P (regno))
   +    return regno - CR0_REGNO + 86;
   +  if (regno == XER_REGNO)
   +    return 101;
   +  if (ALTIVEC_REGNO_P (regno))
   +    return regno - FIRST_ALTIVEC_REGNO + 1124;
   +  if (regno == VRSAVE_REGNO)
   +    return 356;
   +  if (regno == VSCR_REGNO)
   +    return 67;
   +  if (regno == SPE_ACC_REGNO)
   +    return 99;
   +  if (regno == SPEFSCR_REGNO)
   +    return 612;
   +  /* SPE high reg number.  We get these values of regno from
   +     rs6000_dwarf_register_span.  */
   +  if (regno >= 1200 && regno < 1232)
   +    return regno;
   +
   +  abort ();
   +}
   +
    #include "gt-rs6000.h"
   Index: gcc/config/rs6000/rs6000.h
   ===================================================================
   RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
   retrieving revision 1.303
   diff -u -p -r1.303 rs6000.h
   --- gcc/config/rs6000/rs6000.h	31 Dec 2003 00:25:51 -0000	1.303
   +++ gcc/config/rs6000/rs6000.h	6 Jan 2004 15:09:42 -0000
   @@ -811,19 +811,27 @@ extern enum rs6000_nop_insertion rs6000_
    /* This must be included for pre gcc 3.0 glibc compatibility.  */
    #define PRE_GCC3_DWARF_FRAME_REGISTERS 77

   -/* Add 32 dwarf columns for synthetic SPE registers.  The SPE
   -   synthetic registers are 113 through 145.  */
   +/* Add 32 dwarf columns for synthetic SPE registers.  */
    #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)

   -/* The SPE has an additional 32 synthetic registers starting at 1200.
   -   We must map them here to sane values in the unwinder to avoid a
   -   huge hole in the unwind tables.
   +/* The SPE has an additional 32 synthetic registers, with DWARF debug
   +   info numbering for these registers starting at 1200.  While eh_frame
   +   register numbering need not be the same as the debug info numbering,
   +   we choose to number these regs for eh_frame at 1200 too.  This allows
   +   future versions of the rs6000 backend to add hard registers and
   +   continue to use the gcc hard register numbering for eh_frame.  If the
   +   extra SPE registers in eh_frame were numbered starting from the
   +   current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
   +   changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
   +   avoid invalidating older SPE eh_frame info.

   -   FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
   -   the VRSAVE SPR (SPR256) assigned to register 356.  When AltiVec EH
   -   is verified to be working, this macro should be changed
   -   accordingly.  */
   -#define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
   +   We must map them here to avoid huge unwinder tables mostly consisting
   +   of unused space.  */ 
   +#define DWARF_REG_TO_UNWIND_COLUMN(r) \
   +  ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
   +
   +/* Use gcc hard register numbering for eh_frame.  */
   +#define DWARF_FRAME_REGNUM(REGNO) (REGNO)

    /* 1 for registers that have pervasive standard uses
       and are not available for the register allocator.
   Index: gcc/config/rs6000/sysv4.h
   ===================================================================
   RCS file: /cvs/gcc/gcc/gcc/config/rs6000/sysv4.h,v
   retrieving revision 1.143
   diff -u -p -r1.143 sysv4.h
   --- gcc/config/rs6000/sysv4.h	29 Nov 2003 03:08:12 -0000	1.143
   +++ gcc/config/rs6000/sysv4.h	6 Jan 2004 14:41:45 -0000
   @@ -742,6 +742,8 @@ extern int fixuplabelno;
    /* Historically we have also supported stabs debugging.  */
    #define DBX_DEBUGGING_INFO 1

   +#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
   +
    #define TARGET_ENCODE_SECTION_INFO  rs6000_elf_encode_section_info
    #define TARGET_IN_SMALL_DATA_P  rs6000_elf_in_small_data_p
    #define TARGET_SECTION_TYPE_FLAGS  rs6000_elf_section_type_flags

   -- 
   Alan Modra
   IBM OzLabs - Linux Technology Centre

Alan,

If I read your patch correctly, this fixes normal DWARF 2 debugging
info to use the official System V register numbers, but lets GCC
continue to use its own numbering for the Call Frame Info (CFI) in
both the .eh_frame and .debug_frame sections.  This won't work for GDB
since it assumes that CFI uses the same register number encoding as
all the other DWARF 2 debug information.

Mark