From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3222 invoked by alias); 18 May 2002 11:18:00 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 3173 invoked from network); 18 May 2002 11:17:57 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 18 May 2002 11:17:57 -0000 Received: by fw-cam.cambridge.arm.com; id MAA08905; Sat, 18 May 2002 12:17:56 +0100 (BST) Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma008868; Sat, 18 May 02 12:17:34 +0100 Received: from cam-mail2.cambridge.arm.com (cam-mail2.cambridge.arm.com [172.16.1.91]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id MAA11963; Sat, 18 May 2002 12:17:33 +0100 (BST) Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id MAA27270; Sat, 18 May 2002 12:17:33 +0100 (BST) Message-Id: <200205181117.MAA27270@cam-mail2.cambridge.arm.com> To: Andrew Cagney cc: gdb-patches@sources.redhat.com, Richard.Earnshaw@arm.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: [wip/cagney_regbuf-20020515-branch] Introduce regcache_move() In-reply-to: Your message of "Fri, 17 May 2002 12:36:12 EDT." <3CE5317C.6050609@cygnus.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Sat, 18 May 2002 04:18:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-05/txt/msg00780.txt.bz2 ac131313@cygnus.com said: > I suspect RichardE will come up with something for > {read,write}_register_bytes :-) Hmm, no. The more I look into read/write_register bytes the more that I'm forced to the conclusion that it is just irredeemably broken when used by gdb-core. Consider executing the following statement on an ARM debug session with the arm_apcs_32 variable set to zero. (gdb) set $pc=main In this mode the register r15 (the real PC register) is a combination of the two pseudo registers $pc and $cpsr (the program status register), but gdb-core doesn't know anything about this. However, gdb-core currently performs the above asignment in valops.c by using the write_register_bytes call with REGISTER_BYTE($pc) as the offset into the regcache. REGISTER_BYTE(reg) must always return something useful or gdb will just crash, so we are forced to return the address of the raw R15 value in the cache. Write_register_bytes will then overwrite the raw value in the cache without any regard to the masking operations that should be occuring when updating R15; the CPSR bits in the PC are just clobbered and we are left with a broken value in the R15 register. Conclusion: write_register_bytes is so broken that if gdb-core continues to use it I shall have to have separate cache entries for the different bits of R15 and then make the target code do the merging -- this is substantially what the existing code in CVS does, but what I've been trying to move away from (since currently two regcache entries can refer to R15). R.