From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22496 invoked by alias); 18 May 2002 10:55:48 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 22464 invoked from network); 18 May 2002 10:55:45 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 18 May 2002 10:55:45 -0000 Received: by fw-cam.cambridge.arm.com; id LAA04274; Sat, 18 May 2002 11:55:44 +0100 (BST) Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma004165; Sat, 18 May 02 11:55:02 +0100 Received: from cam-mail2.cambridge.arm.com (cam-mail2.cambridge.arm.com [172.16.1.91]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id LAA10244; Sat, 18 May 2002 11:55:02 +0100 (BST) Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id LAA26201; Sat, 18 May 2002 11:55:01 +0100 (BST) Message-Id: <200205181055.LAA26201@cam-mail2.cambridge.arm.com> To: Michael Snyder cc: Richard.Earnshaw@arm.com, Andrew Cagney , gdb-patches@sources.redhat.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: [patch/rfc] Revise REGISTER_SIM_REGNO() In-reply-to: Your message of "Fri, 17 May 2002 10:35:13 PDT." <3CE53F51.BEC03B6D@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Sat, 18 May 2002 03:55:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-05/txt/msg00778.txt.bz2 > > I need a way the target vector to let REGISTER_NAME() know that the > > register is "unavailable this session", so that it can return an empty > > string for the register; so that gdb won't think it exists at all. > > > I see. This is something that depends on both the arch and the target. Yep, the arch says what registers a processor has, the target says which of those it can supply. Of course, you will only get a useful debugging session if the two overlap sufficiently. I suspect that it will be quite common for the arch to describe registers that are only available when the processor is running in a privileged mode; clearly you don't need those to debug a user-level program, but they can be very helpful when trying to debug an OS. Certainly this is the way I'd like to describe the views of ARM processors. R.