RFC: ARM simulator coredump

[Fred Fish <fnf@fred.ninemoons.com>]

The ARM simulator is dumping core during gdb testing for arm-elf:

  Program received signal SIGSEGV, Segmentation fault.
  0x08147074 in XScale_cp14_read_reg (state=0x8299ff0, reg=0, value=0x0) at /src/sourceware/gdb/src/sim/arm/armcopro.c:981
  981       * value = read_cp14_reg (reg);

This patch seems to work, but I've not really checked it too carefully
for correctness.  Can whomever is responsible for the ARM simulator
look it over please?  Thanks.

-Fred

Index: armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.25
diff -u -p -r1.25 armemu.c
--- armemu.c	2001/10/18 12:20:47	1.25
+++ armemu.c	2002/01/09 22:59:41
@@ -544,15 +544,16 @@ ARMul_Emulate26 (ARMul_State * state)
       /* Handle the Clock counter here.  */
       if (state->is_XScale)
 	{
-	  ARMword cp14r0 = state->CPRead[14] (state, 0, 0);
+	  ARMword cp14r0;
+	  int ok = state->CPRead[14] (state, 0, &cp14r0);
 
-	  if (cp14r0 && ARMul_CP14_R0_ENABLE)
+	  if (ok && ARMul_CP14_R0_ENABLE)
 	    {
 	      unsigned long newcycles, nowtime = ARMul_Time(state);
 
 	      newcycles = nowtime - state->LastTime;
 	      state->LastTime = nowtime;
-	      if (cp14r0 && ARMul_CP14_R0_CCD)
+	      if (ok && ARMul_CP14_R0_CCD)
 	        {
 		  if (state->CP14R0_CCD == -1)
 		    state->CP14R0_CCD = newcycles;
@@ -576,7 +577,7 @@ check_PMUintr:
 		  cp14r0 |= ARMul_CP14_R0_FLAG2;
 		  (void) state->CPWrite[14] (state, 0, cp14r0);
 
-		  cp14r1 = state->CPRead[14] (state, 1, 0);
+		  ok = state->CPRead[14] (state, 1, &cp14r1);
 
 		  /* Coded like this for portability.  */
 		  while (newcycles)
@@ -593,7 +594,8 @@ check_PMUintr:
 		  (void) state->CPWrite[14] (state, 1, cp14r1);
 		  if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
 		    {
-		      if (state->CPRead[13] (state, 8, 0)
+		      ARMword temp;
+		      if (state->CPRead[13] (state, 8, &temp)
 			&& ARMul_CP13_R8_PMUS)
 		        ARMul_Abort (state, ARMul_FIQV);
 		      else
Index: arminit.c
===================================================================
RCS file: /cvs/src/src/sim/arm/arminit.c,v
retrieving revision 1.7
diff -u -p -r1.7 arminit.c
--- arminit.c	2001/04/18 16:39:37	1.7
+++ arminit.c	2002/01/09 22:59:41
@@ -302,14 +302,20 @@ ARMul_Abort (ARMul_State * state, ARMwor
       SETABORT (IBIT, SVC26MODE, isize);
       break;
     case ARMul_IRQV:		/* IRQ */
-      if (!state->is_XScale
-	  || (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_IRQ))
-        SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
+      {
+	ARMword temp;
+	(void) state->CPRead[13](state, 0, &temp);
+	if (!state->is_XScale || (temp & ARMul_CP13_R0_IRQ))
+	  SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
+      }
       break;
     case ARMul_FIQV:		/* FIQ */
-      if (!state->is_XScale
-	  || (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_FIQ))
-        SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
+      {
+	ARMword temp;
+	(void) state->CPRead[13](state, 0, &temp);
+	if (!state->is_XScale || (temp & ARMul_CP13_R0_FIQ))
+	  SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
+      }
       break;
     }
   if (ARMul_MODE32BIT)