From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id oE4gLQnm/WNbeAAAWB0awg (envelope-from ) for ; Tue, 28 Feb 2023 06:31:21 -0500 Received: by simark.ca (Postfix, from userid 112) id B62221E223; Tue, 28 Feb 2023 06:31:21 -0500 (EST) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=B+7+/BLr; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 1CD121E128 for ; Tue, 28 Feb 2023 06:31:21 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C5790385086A for ; Tue, 28 Feb 2023 11:31:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C5790385086A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1677583880; bh=7V/5xAd4XFNukQAAHSqw7a2TBzM2Os1ze5URejpmePo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=B+7+/BLrp74LHpkMV56bFuh2lBE0WUcCJ+lpTpzqR+jQ8KaNbdkunsUYey3LhRLEp ZpSR4+6cWwi1aONjac3tcaLcDwKt+TZUYcKL+GfhvTlukEk1UAm7L8RRk8zzmm2iXv CDClnEGj+1gO+/09aFdYV+a/VbEehCo46sJecQxg= Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 81467384D16E for ; Tue, 28 Feb 2023 11:30:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 81467384D16E X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="313785189" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="313785189" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2023 03:30:59 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="623992239" X-IronPort-AV: E=Sophos;i="5.98,221,1673942400"; d="scan'208";a="623992239" Received: from ultl2604.iul.intel.com (HELO localhost) ([172.28.48.47]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2023 03:30:58 -0800 To: gdb-patches@sourceware.org Subject: [PATCH 21/26] gdbserver: use REG_UNKNOWN for a regcache's register statuses Date: Tue, 28 Feb 2023 12:28:19 +0100 Message-Id: <1fcffbf8ffd62b07585baebff38b66f10ec0a112.1677582745.git.tankut.baris.aktemur@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tankut Baris Aktemur via Gdb-patches Reply-To: Tankut Baris Aktemur Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" When a regcache is initialized, the values of registers are not fetched yet. Thus, initialize the register statuses to REG_UNKNOWN instead of REG_UNAVAILABLE, because the latter rather means "we attempted to fetch but could not obtain the value". The definitions of the reg status enums (from gdbsupport/common-regcache.h) as a reminder: /* The register value is not in the cache, and we don't know yet whether it's available in the target (or traceframe). */ REG_UNKNOWN = 0, /* The register value is valid and cached. */ REG_VALID = 1, /* The register value is unavailable. E.g., we're inspecting a traceframe, and this register wasn't collected. Note that this "unavailable" is different from saying the register does not exist in the target's architecture --- in that case, the target should have given us a target description that does not include the register in the first place. */ REG_UNAVAILABLE = -1 Similarly, when the regcache is invalidated, change all the statuses back to REG_UNKNOWN. --- gdbserver/regcache.cc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gdbserver/regcache.cc b/gdbserver/regcache.cc index 09ea58bdbd6..2befb30e337 100644 --- a/gdbserver/regcache.cc +++ b/gdbserver/regcache.cc @@ -64,9 +64,17 @@ regcache::fetch () switch_to_thread (this->thread); /* Invalidate all registers, to prevent stale left-overs. */ - memset (register_status, REG_UNAVAILABLE, tdesc->reg_defs.size ()); + discard (); fetch_inferior_registers (this, -1); registers_fetched = true; + + /* Make sure that the registers that could not be fetched are + now unavailable. */ + for (int i = 0; i < tdesc->reg_defs.size (); ++i) + { + if (register_status[i] == REG_UNKNOWN) + set_register_status (i, REG_UNAVAILABLE); + } } } @@ -128,6 +136,9 @@ regcache_invalidate (void) void regcache::discard () { +#ifndef IN_PROCESS_AGENT + memset ((void *) register_status, REG_UNKNOWN, tdesc->reg_defs.size ()); +#endif registers_fetched = false; } @@ -148,8 +159,7 @@ regcache::initialize (const target_desc *tdesc, this->registers_owned = true; this->register_status = (enum register_status *) xmalloc (tdesc->reg_defs.size ()); - memset ((void *) this->register_status, REG_UNAVAILABLE, - tdesc->reg_defs.size ()); + discard (); #else gdb_assert_not_reached ("can't allocate memory from the heap"); #endif -- 2.25.1 Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928