From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id oCrYOVmRCGCIZAAAWB0awg (envelope-from ) for ; Wed, 20 Jan 2021 15:23:53 -0500 Received: by simark.ca (Postfix, from userid 112) id 55F0D1EF80; Wed, 20 Jan 2021 15:23:52 -0500 (EST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=DKIM_SIGNED,MAILING_LIST_MULTI, RDNS_NONE,T_DKIM_INVALID,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 4A7C91E590 for ; Wed, 20 Jan 2021 15:23:51 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 553183971C1E; Wed, 20 Jan 2021 20:23:37 +0000 (GMT) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id D3B903971823 for ; Wed, 20 Jan 2021 20:23:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D3B903971823 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andrew.burgess@embecosm.com Received: by mail-wr1-x429.google.com with SMTP id a12so24293078wrv.8 for ; Wed, 20 Jan 2021 12:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Uwa3jqXP5FvGywMbWLzWAi4lPlu+r3orI3lC4bORr7o=; b=UK2WOCcCu87Ebupz+7xGw7/ymNLr1ZEPaplvqdgX2QHU+O4ZBNI5LJCG6H5knhVxnl bjkcQpJi6u/75PtxDu99/3JY49Lh+gVZM3IzIWI0eDLXh5HugANVaVSZf6SREUzHFPAI Kjk0seo0WN97sm4gUWiavzVAy/o//1bD+OXmTPPbYpex9YikjitlrI2Y1WoBPfPlxy1a MZAMUE6R4RMpvIof0CEdsONy3N3fam3LX7phlj6T38+LxuRtJ99s2D2EpQ3l6WXtgzs8 qhqWoBlazkqbtnku6PyZ7pxTLlL/E46qJGlPXnFM5WXchFYrLIGBCq8o6h4diFSRxNQj GSLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uwa3jqXP5FvGywMbWLzWAi4lPlu+r3orI3lC4bORr7o=; b=RbEZctWqEFWniLgpsPW5zq4MSJpAveHGqTErZhbJNaeOoQSLh2VNZnMyDLNOfnkXiB Io52GTXzWpKPIRSiIsIJizaNUIfXjNmYYkmmOUijs4jAgmqT/EW0HmCAOu4EN+WNwmnP V8kz88LDYOKteiyRuEA8pm8JwOks4gC4RZ/Me5SUicqMjQRwDwTpHKr86AkP9FTMrBTv e2EKz6y0NKphYzvAiecJD+WksJhM58RmGSreJavIEaRMe+nDq4Ec07ihZNhCSzRagU6B kY4gFNwzfVmePGcoEIGpcT1B8o3I7JF1d5FWCrTp8SeeGdeJ61cFPe0DeMkijiJOq1gG 30/A== X-Gm-Message-State: AOAM531evYc8oiY6dInv7bNTnKfOAK7uNSz2l4JJKjJ1hsWcDLK6/8AA yFRxF5CZkHAnoc5MEIp9bvxYqoRLMUTEjA== X-Google-Smtp-Source: ABdhPJyQWqUkhFbBIEu7r9lY6JTMkC9r/BUWdEK3jC38nuuuxD6WQRH9IXJWOQuGMacuRkP7wvMDyQ== X-Received: by 2002:adf:f747:: with SMTP id z7mr3546091wrp.384.1611174212591; Wed, 20 Jan 2021 12:23:32 -0800 (PST) Received: from localhost (host86-180-62-229.range86-180.btcentralplus.com. [86.180.62.229]) by smtp.gmail.com with ESMTPSA id a12sm6554792wrh.71.2021.01.20.12.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 12:23:32 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org, binutils@sourceware.org Subject: [PATCHv2 9/9] gdb/arm: add support for bare-metal core dumps Date: Wed, 20 Jan 2021 20:23:15 +0000 Message-Id: <1d767ed944205b58d1df09dd1aa218a6fabcc7f5.1611172468.git.andrew.burgess@embecosm.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Hederstierna Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" This commit is just a trimmed down version of Fredrik's patch (link below), updated to fit in with my new common core dumping code. As a significant piece of work Fredrik would need a copyright assignment in place before this could be merged. I don't know if that is the case or not. As with the RISC-V patch (#5) the documentation of the core file format is given in the commit message, but it really needs a "better" home. Unlike RISC-V, I don't know where that home is for ARM. I would prefer if most feedback on the documentation was given on the RISC-V patch (#5 in this series), unless you're pointing out an error that is specific just to this patch. I have checked that this code builds, but otherwise I've done no testing on this at all. I assume Fredrik gave this some testing before posting, but I have mucked about with things, so I'm sure any mistakes are mine. Thanks, Andrew --- This commit adds support for bare metal core dumps on the ARM target, and is based off of this patch submitted to the mailing list: https://sourceware.org/pipermail/gdb-patches/2020-October/172845.html Compared to the version linked above this version is updated to take account of recent changes to the core dump infrastructure in GDB, there is now more shared infrastructure for core dumping within GDB, and also some common bare metal core dumping infrastructure. As a result this patch is smaller than the original proposed patch. Further, the original patch included some unrelated changes to the simulator that have been removed from this version. I have written a ChangeLog entry as the original patch was missing one. I have done absolutely no testing of this patch. It is based on the original submitted patch, which I assume was tested, but after my modifications things might have been broken. The cores dump format is based around generating an ELF containing sections for the writable regions of memory that a user could be using. Which regions are dumped rely on GDB's existing common core dumping code, GDB will attempt to figure out the stack and heap as well as copying out writable data sections as identified by the original ELF. Register information is added to the core dump using notes, just as it is for Linux of FreeBSD core dumps. The note types used consist of the 2 basic types you would expect in a OS based core dump, NT_PRPSINFO, NT_PRSTATUS, along with the architecture specific NT_ARM_VFP note. The data layouts for each note type are described blow, in all case, all padding fields should be set to zero. Note NT_PRPSINFO is optional. Its data layout is: struct prpsinfo_t { uint8_t padding[28]; char fname[16]; char psargs[80]; } Field 'fname' - null terminated string consisting of the basename of (up to the fist 15 characters of) the executable. Any additional space should be set to zero. If there's no executable name then this field can be set to all zero. Field 'psargs' - a null terminated string up to 80 characters in length. Any additional space should be filled with zero. This field contains the full executable path and any arguments passed to the executable. If there's nothing sensible to write in this field then fill it with zero. Note NT_PRSTATUS is required, its data layout is: struct prstatus_t { uint8_t padding_1[12]; uint16_t sig; uint8_t padding_2[10]; uint32_t thread_id; uint8_t padding_3[44]; uint32_t gregs[18]; } Field 'sig' - the signal that stopped this thread. Its implementation defined what this field actually means. Within GDB this will be the signal number that the remote target reports as the stop reason for this thread. Field 'thread_is' - the thread id for this thread, its implementation defined what this field actually means. Within GDB this will be thread thread-id that is assigned to each remote thread. Field 'gregs' - holds the general purpose registers $a1 through to $pc at indices 0 to 15. At index 16 the program status register. Index 17 should be set to zero. Note NT_ARM_VFP is optional, its data layout is: armvfp_t { uint64_t regs[32]; uint32_t fpscr; } Field 'regs' - holds the 32 d-registers 0 to 31 in order. Field 'fpscr' - holds the fpscr register. The rules for ordering the notes is the same as for Linux. The NT_PRSTATUS note must come before any other notes about additional register sets. And for multi-threaded targets all registers for a single thread should be grouped together. This is because only NT_PRSTATUS includes a thread-id, all additional register notes after a NT_PRSTATUS are assumed to belong to the same thread until a different NT_PRSTATUS is seen. gdb/ChangeLog: PR gdb/14383 * Makefile.in (ALL_TARGET_OBS): Add arm-none-tdep.o. (ALLDEPFILES): Add arm-none-tdep.c * arm-none-tdep.c: New file. * configure.tgt (arm*-*-*): Add arm-none-tdep.o to cpu_obs. --- gdb/ChangeLog | 9 ++ gdb/Makefile.in | 2 + gdb/arm-none-tdep.c | 208 ++++++++++++++++++++++++++++++++++++++++++++ gdb/configure.tgt | 3 +- 4 files changed, 221 insertions(+), 1 deletion(-) create mode 100644 gdb/arm-none-tdep.c diff --git a/gdb/Makefile.in b/gdb/Makefile.in index 5f88b6a78cf..c40dd7d4688 100644 --- a/gdb/Makefile.in +++ b/gdb/Makefile.in @@ -726,6 +726,7 @@ ALL_TARGET_OBS = \ arm-fbsd-tdep.o \ arm-linux-tdep.o \ arm-netbsd-tdep.o \ + arm-none-tdep.o \ arm-obsd-tdep.o \ arm-pikeos-tdep.o \ arm-symbian-tdep.o \ @@ -2167,6 +2168,7 @@ ALLDEPFILES = \ arm-linux-tdep.c \ arm-netbsd-nat.c \ arm-netbsd-tdep.c \ + arm-none-tdep.c \ arm-obsd-tdep.c \ arm-symbian-tdep.c \ arm-tdep.c \ diff --git a/gdb/arm-none-tdep.c b/gdb/arm-none-tdep.c new file mode 100644 index 00000000000..199ac652129 --- /dev/null +++ b/gdb/arm-none-tdep.c @@ -0,0 +1,208 @@ +/* none on ARM target support. + + Copyright (C) 2020 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "defs.h" +#include "arm-tdep.h" +#include "arch-utils.h" +#include "regcache.h" +#include "elf-bfd.h" +#include "regset.h" +#include "none-tdep.h" +#include "user-regs.h" + +/* Core file and register set support. */ +#define ARM_NONE_SIZEOF_GREGSET (18 * ARM_INT_REGISTER_SIZE) + +/* Support VFP register format. */ +#define ARM_NONE_SIZEOF_VFP (32 * 8 + 4) + +/* The index to access CSPR in user_regs as defined in GLIBC. */ +#define ARM_NONE_CPSR_GREGNUM 16 + +/* Supply register REGNUM from buffer GREGS_BUF (length LEN bytes) into + REGCACHE. If REGNUM is -1 then supply all registers. The set of + registers that this function will supply is limited to the general + purpose registers. + + The layout of the registers here is based on the ARM GNU/Linux + layout. */ + +static void +arm_none_supply_gregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *gregs_buf, size_t len) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + const gdb_byte *gregs = (const gdb_byte *) gregs_buf; + + for (int regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++) + if (regnum == -1 || regnum == regno) + regcache->raw_supply (regno, gregs + ARM_INT_REGISTER_SIZE * regno); + + if (regnum == ARM_PS_REGNUM || regnum == -1) + { + if (arm_apcs_32) + regcache->raw_supply (ARM_PS_REGNUM, + gregs + ARM_INT_REGISTER_SIZE + * ARM_NONE_CPSR_GREGNUM); + else + regcache->raw_supply (ARM_PS_REGNUM, + gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM); + } + + if (regnum == ARM_PC_REGNUM || regnum == -1) + { + gdb_byte pc_buf[ARM_INT_REGISTER_SIZE]; + + CORE_ADDR reg_pc + = extract_unsigned_integer (gregs + ARM_INT_REGISTER_SIZE + * ARM_PC_REGNUM, + ARM_INT_REGISTER_SIZE, byte_order); + reg_pc = gdbarch_addr_bits_remove (gdbarch, reg_pc); + store_unsigned_integer (pc_buf, ARM_INT_REGISTER_SIZE, byte_order, + reg_pc); + regcache->raw_supply (ARM_PC_REGNUM, pc_buf); + } +} + +/* Collect register REGNUM from REGCACHE and place it into buffer GREGS_BUF + (length LEN bytes). If REGNUM is -1 then collect all registers. The + set of registers that this function will collect is limited to the + general purpose registers. + + The layout of the registers here is based on the ARM GNU/Linux + layout. */ + +static void +arm_none_collect_gregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *gregs_buf, size_t len) +{ + gdb_byte *gregs = (gdb_byte *) gregs_buf; + + for (int regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++) + if (regnum == -1 || regnum == regno) + regcache->raw_collect (regno, + gregs + ARM_INT_REGISTER_SIZE * regno); + + if (regnum == ARM_PS_REGNUM || regnum == -1) + { + if (arm_apcs_32) + regcache->raw_collect (ARM_PS_REGNUM, + gregs + ARM_INT_REGISTER_SIZE + * ARM_NONE_CPSR_GREGNUM); + else + regcache->raw_collect (ARM_PS_REGNUM, + gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM); + } + + if (regnum == ARM_PC_REGNUM || regnum == -1) + regcache->raw_collect (ARM_PC_REGNUM, + gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM); +} + +/* Supply VFP registers from REGS_BUF into REGCACHE. */ + +static void +arm_none_supply_vfp (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *regs_buf, size_t len) +{ + const gdb_byte *regs = (const gdb_byte *) regs_buf; + + if (regnum == ARM_FPSCR_REGNUM || regnum == -1) + regcache->raw_supply (ARM_FPSCR_REGNUM, regs + 32 * 8); + + for (int regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++) + if (regnum == -1 || regnum == regno) + regcache->raw_supply (regno, regs + (regno - ARM_D0_REGNUM) * 8); +} + +/* Collect VFP registers from REGCACHE into REGS_BUF. */ + +static void +arm_none_collect_vfp (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *regs_buf, size_t len) +{ + gdb_byte *regs = (gdb_byte *) regs_buf; + + if (regnum == ARM_FPSCR_REGNUM || regnum == -1) + regcache->raw_collect (ARM_FPSCR_REGNUM, regs + 32 * 8); + + for (int regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++) + if (regnum == -1 || regnum == regno) + regcache->raw_collect (regno, regs + (regno - ARM_D0_REGNUM) * 8); +} + +/* The general purpose register set. */ + +static const struct regset arm_none_gregset = + { + nullptr, arm_none_supply_gregset, arm_none_collect_gregset + }; + +/* The VFP register set. */ + +static const struct regset arm_none_vfpregset = + { + nullptr, arm_none_supply_vfp, arm_none_collect_vfp + }; + +/* Iterate over core file register note sections. */ + +static void +arm_none_iterate_over_regset_sections (struct gdbarch *gdbarch, + iterate_over_regset_sections_cb *cb, + void *cb_data, + const struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + cb (".reg", ARM_NONE_SIZEOF_GREGSET, ARM_NONE_SIZEOF_GREGSET, + &arm_none_gregset, nullptr, cb_data); + + if (tdep->vfp_register_count > 0) + cb (".reg-arm-vfp", ARM_NONE_SIZEOF_VFP, ARM_NONE_SIZEOF_VFP, + &arm_none_vfpregset, "VFP floating-point", cb_data); +} + +/* Initialize ARM bare-metal ABI info. */ + +static void +arm_none_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + none_init_abi (gdbarch); + + /* Iterate over registers for reading and writing bare metal ARM core + files. */ + set_gdbarch_iterate_over_regset_sections + (gdbarch, arm_none_iterate_over_regset_sections); +} + +/* Initialize ARM bare-metal target support. */ + +void _initialize_arm_none_tdep (); +void +_initialize_arm_none_tdep () +{ + gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_NONE, + arm_none_init_abi); +} diff --git a/gdb/configure.tgt b/gdb/configure.tgt index ad88ddd9302..4f3b9df90d7 100644 --- a/gdb/configure.tgt +++ b/gdb/configure.tgt @@ -65,7 +65,8 @@ arc*-*-*) arm*-*-*) cpu_obs="aarch32-tdep.o arch/aarch32.o arch/arm.o \ - arch/arm-get-next-pcs.o arm-tdep.o";; + arch/arm-get-next-pcs.o arm-tdep.o arm-none-tdep.o" + ;; hppa*-*-*) # Target: HP PA-RISC -- 2.25.4