From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28247 invoked by alias); 23 Jul 2018 17:25:18 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 759 invoked by uid 89); 23 Jul 2018 17:25:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,SPF_PASS autolearn=unavailable version=3.3.2 spammy=H*UA:Zimbra, H*x:Zimbra, H*M:zimbra, bare X-HELO: dedi548.your-server.de Received: from dedi548.your-server.de (HELO dedi548.your-server.de) (85.10.215.148) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Jul 2018 17:24:42 +0000 Received: from [78.46.172.3] (helo=sslproxy06.your-server.de) by dedi548.your-server.de with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.85_2) (envelope-from ) id 1fheZb-0008Dq-P9; Mon, 23 Jul 2018 19:24:39 +0200 Received: from [82.135.62.35] (helo=mail.embedded-brains.de) by sslproxy06.your-server.de with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.89) (envelope-from ) id 1fheZb-000EM9-EF; Mon, 23 Jul 2018 19:24:39 +0200 Received: from localhost (localhost.localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 5D1D32A1685; Mon, 23 Jul 2018 19:24:46 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 3HhZw6NLNYpj; Mon, 23 Jul 2018 19:24:44 +0200 (CEST) Received: from localhost (localhost.localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 24D032A1686; Mon, 23 Jul 2018 19:24:44 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id yfflYoV2v4fy; Mon, 23 Jul 2018 19:24:44 +0200 (CEST) Received: from zimbra.eb.localhost (zimbra.eb.localhost [192.168.96.204]) by mail.embedded-brains.de (Postfix) with ESMTP id 0BE282A1685; Mon, 23 Jul 2018 19:24:44 +0200 (CEST) Date: Mon, 23 Jul 2018 17:25:00 -0000 From: Sebastian Huber To: Jim Wilson Cc: gdb-patches@sourceware.org, Andrew Burgess Message-ID: <1830811266.24706.1532366683342.JavaMail.zimbra@embedded-brains.de> In-Reply-To: References: <20180717001241.25908-1-jimw@sifive.com> <71103f9b-f83b-7e68-1d56-f30038473936@embedded-brains.de> Subject: Re: [PATCH] RISC-V: Don't decrement pc after break. MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2018-07/txt/msg00666.txt.bz2 ----- Am 23. Jul 2018 um 17:38 schrieb Jim Wilson jimw@sifive.com: > On Mon, Jul 23, 2018 at 3:30 AM, Sebastian Huber > wrote: >> Hello Jim, >> >> this patch broke debugging with Qemu (qemu-system-riscv64, Git commit >> 6598f0cdad6acc6674c4f060fa46e537228c2c47). The GDB error message is: >> >> Register 3921 is not available > > I don't understand how rtems debugging could have worked without this > patch. 3921 minus 65 in hex is 0xf10 which is the legacy misa. The > legacy misa is checked only if a read of the v1.9.1 misa fails. If > the read of both the v1.9.1 misa and the legacy misa fails, then you > get a confusing error stating that register 3921 is not available. > But the real problem is that both misa reads failed. The ISA spec > says that misa must exist and be readable, although an implementation > is allowed to return 0 when it is read. Gdb uses misa to determine > target features. Gdb does handle the 0 read case by deducing info > from ELF header flags instead of the misa register. > > If you have a rtems target support, then it must handle reading the > misa register. If is OK to just return 0. That is what my linux port > does for now. At some point I may try adding a linux kernel patch to > add ptrace support for reading misa. If rtems is running in machine > mode, you can probably read misa directly. Otherwise, you would need > something like a linux ptrace to read it. For embedded targets using > openocd, they can just read misa directly. RTEMS is more or less just a bare metal ELF target with a special Newlib configuration. I think the question is, why it worked at all on bare metal ELF RISC-V targets before. > > The problem with misa is easy to miss, as gdb only tries to read misa > if you execute a command that requires info about the target, such as > trying to use hardware floating point. Actually, one of my other > patches, the one to remove the pc decrement after a break, modified > the code so that we try to read misa when checking to see if > compressed breakpoints could be used. Before it was only checking ELF > headers for this, which wasn't right. This is probably the patch that > exposed the bug in your rtems target support. This could be also a Qemu bug. I have to check this with the debugger tomorrow. The misa should be returned by Qemu in csr_read_helper() (target/riscv/op_helper.c). A "info registers" for example returns only the standard registers. For the CSR registers I get "not available".