From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by sourceware.org (Postfix) with ESMTPS id D49783896817 for ; Wed, 6 May 2020 02:56:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D49783896817 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nelson.chu@sifive.com Received: by mail-pj1-x1033.google.com with SMTP id h12so1916761pjz.1 for ; Tue, 05 May 2020 19:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UpFulGVFzTZzd0qJGU9ezc61aYAf6dm7sySK52vweM0=; b=MY9FGCMOlh1MZNtrIGxsitKfvGBVNIWtgJjsJD5NO/Z4dhzxZvzm6eCEKt3bUWmyAt XlYOjN8u51uggxXNjFHSKQroijucdbiq/yxOj5IdIRiZ1C37iDxYFCUY5ugpZblQ/43+ Yk04JRYJzOWda+RxU8mN3CTOE5L1qWxRUGIgF6diZDGQfhRJVtVGqFP00/Q9b7qT7pln qqBAnTLviFWDVPmmwrWc5DqrAZiqt9e9ahBb5blYSUHETGhU6duAAQUqxxb7HRy153yP +7Sj9qgcxgoJS+fhDoOVdcHk1OxYaDZP4w5q1vFR2iXldazZB2/gdskgtccXZeV9I6Xt daQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UpFulGVFzTZzd0qJGU9ezc61aYAf6dm7sySK52vweM0=; b=Rc8gg8QVnhrHCsWq/HgIzT7E8Loh3acKQ0UL1/BGzP1Goyyh7kR2jXm3cyppPFro0K PE9ZEz828c6OaWxfJk1LCviskRAYMOM1i1Mg3Z4rHYxhykkAlH7gud5f5yjQZi5rf1zo 7hFYIwpqUu2hXgOn/5GFXmEspZ7nT4rryo5XLn3QKOldX1Sr3PYDkHRmWDt5TMEz32Xe q9ArSzEOXRAWWRNZdxGkK+VR/5ax2YtNtX3ETB9+HRRsRaL7lUEnVgN02GOf6S5ivm4k 53pjik0mDhTtpl5d1bb0QKHiOdtl829eaKk/LviZStrPkuQmC4Rx+yfm414YW8Yp1TaQ dmMg== X-Gm-Message-State: AGi0Pub7mCoaelTsZCK9e6g8pRSdTnudy8bB2VyhufSkkHZVMLbhLqqZ qX9SE2qCrgoKRRQ+IQKmBQXlTg== X-Google-Smtp-Source: APiQypIUon2IJ5zfd5RdtP/JioUkxdT9nC0oJ1gjQktz74a7l+w9PZ4MuC9rWvlRyVquAPatv9WOKA== X-Received: by 2002:a17:902:aa4b:: with SMTP id c11mr5054064plr.211.1588733759644; Tue, 05 May 2020 19:55:59 -0700 (PDT) Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id 141sm222996pfz.171.2020.05.05.19.55.58 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 May 2020 19:55:59 -0700 (PDT) From: Nelson Chu To: binutils@sourceware.org, gdb-patches@sourceware.org Cc: palmer@dabbelt.com, kito.cheng@sifive.com, jimw@sifive.com, andrew@sifive.com, andrew.burgess@embecosm.com, asb@lowrisc.org, maxim.blinov@embecosm.com, nelson.chu@sifive.com Subject: [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable. Date: Tue, 5 May 2020 19:55:45 -0700 Message-Id: <1588733747-18787-8-git-send-email-nelson.chu@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com> References: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com> X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 May 2020 02:56:05 -0000 There are three privilege spec attributes, Tag_RISCV_priv_spec, Tag_RISCV_priv_spec_minor and Tag_RISCV_priv_spec_revision, are used to choose which version of privilege spec you want. You can also use -mpriv-spec option to choose the priv spec, but the priority of ELF attributes is the highest. Beside, we have to make sure all arch and priv attributes are set before any instruction. The Priority of these options, * ELF priv attributes > -mpriv-spec > --with-priv-spec bfd/ * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas/ * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. --- bfd/elfxx-riscv.c | 2 +- bfd/elfxx-riscv.h | 3 + gas/config/tc-riscv.c | 154 ++++++++++++++++++--- gas/testsuite/gas/riscv/attribute-01.d | 3 + gas/testsuite/gas/riscv/attribute-02.d | 3 + gas/testsuite/gas/riscv/attribute-03.d | 3 + gas/testsuite/gas/riscv/attribute-04.d | 3 + gas/testsuite/gas/riscv/attribute-05.d | 4 +- gas/testsuite/gas/riscv/attribute-05.s | 4 +- gas/testsuite/gas/riscv/attribute-06.d | 3 + gas/testsuite/gas/riscv/attribute-07.d | 3 + gas/testsuite/gas/riscv/attribute-08.d | 3 + gas/testsuite/gas/riscv/attribute-09.d | 3 + gas/testsuite/gas/riscv/attribute-10.d | 3 + gas/testsuite/gas/riscv/attribute-unknown.d | 3 + .../gas/riscv/priv-reg-fail-version-1p10.d | 10 +- .../gas/riscv/priv-reg-fail-version-1p11.d | 10 +- .../gas/riscv/priv-reg-fail-version-1p9.d | 10 +- .../gas/riscv/priv-reg-fail-version-1p9p1.d | 11 +- ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 + ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 + ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 + ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s | 4 +- ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s | 4 +- ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d | 4 +- ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 3 + .../ld-riscv-elf/attr-merge-strict-align-01.d | 3 + .../ld-riscv-elf/attr-merge-strict-align-02.d | 3 + .../ld-riscv-elf/attr-merge-strict-align-03.d | 3 + .../ld-riscv-elf/attr-merge-strict-align-04.d | 3 + .../ld-riscv-elf/attr-merge-strict-align-05.d | 3 + 31 files changed, 241 insertions(+), 36 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e025689..d06c2a5 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1650,7 +1650,7 @@ riscv_release_subset_list (riscv_subset_list_t *subset_list) /* Return the number of digits for the input. */ -static size_t +size_t riscv_estimate_digit (unsigned num) { size_t digit = 0; diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h index cbafd28..a3a0862 100644 --- a/bfd/elfxx-riscv.h +++ b/bfd/elfxx-riscv.h @@ -90,6 +90,9 @@ riscv_release_subset_list (riscv_subset_list_t *); extern char * riscv_arch_str (unsigned, const riscv_subset_list_t *); +extern size_t +riscv_estimate_digit (unsigned); + /* ISA extension name class. E.g. "zbb" corresponds to RV_ISA_CLASS_Z, "xargs" corresponds to RV_ISA_CLASS_X, etc. Order is important here. */ diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 6fd1dcf..6e30a06 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -116,22 +116,74 @@ riscv_set_default_isa_spec (const char *s) } /* Set the default_priv_spec, assembler will find the suitable CSR address - according to default_priv_spec. Return 0 if the input priv name isn't + according to default_priv_spec. We will try to check priv attributes if + the input string is NULL. Return 0 if the input priv spec string isn't supported. Otherwise, return 1. */ static int riscv_set_default_priv_spec (const char *s) { enum riscv_priv_spec_class class; - if (!riscv_get_priv_spec_class (s, &class)) + unsigned major, minor, revision; + obj_attribute *attr; + size_t buf_size; + char *buf; + + /* Find the corresponding priv spec class. */ + if (riscv_get_priv_spec_class (s, &class)) + { + default_priv_spec = class; + return 1; + } + + if (s != NULL) { as_bad (_("Unknown default privilege spec `%s' set by " "-mpriv-spec or --with-priv-spec"), s); return 0; } + + /* Try to set the default_priv_spec according to the priv attributes. */ + attr = elf_known_obj_attributes_proc (stdoutput); + major = (unsigned) attr[Tag_RISCV_priv_spec].i; + minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i; + revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i; + + /* The priv attributes setting 0.0.0 is meaningless. We should have set + the default_priv_spec by md_parse_option and riscv_after_parse_args, + so just skip the following setting. */ + if (major == 0 && minor == 0 && revision == 0) + return 1; + + buf_size = riscv_estimate_digit (major) + + 1 /* '.' */ + + riscv_estimate_digit (minor) + + 1; /* string terminator */ + if (revision != 0) + { + buf_size += 1 /* '.' */ + + riscv_estimate_digit (revision); + buf = xmalloc (buf_size); + snprintf (buf, buf_size, "%d.%d.%d", major, minor, revision); + } else - default_priv_spec = class; - return 1; + { + buf = xmalloc (buf_size); + snprintf (buf, buf_size, "%d.%d", major, minor); + } + + if (riscv_get_priv_spec_class (buf, &class)) + { + default_priv_spec = class; + free (buf); + return 1; + } + + /* Still can not find the priv spec class. */ + as_bad (_("Unknown default privilege spec `%d.%d.%d' set by " + "privilege attributes"), major, minor, revision); + free (buf); + return 0; } /* This is the set of options which the .option pseudo-op may modify. */ @@ -319,8 +371,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; /* Indicate we are already assemble any instructions or not. */ static bfd_boolean start_assemble = FALSE; -/* Indicate arch attribute is explictly set. */ -static bfd_boolean explicit_arch_attr = FALSE; +/* Indicate ELF attributes are explictly set. */ +static bfd_boolean explicit_attr = FALSE; /* Macros for encoding relaxation state for RVC branches and far jumps. */ #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ @@ -2495,9 +2547,17 @@ md_assemble (char *str) expressionS imm_expr; bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; - const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); + /* The arch and priv attributes should be set before assembling. */ + if (!start_assemble) + { + start_assemble = TRUE; - start_assemble = TRUE; + /* Set the default_priv_spec according to the priv attributes. */ + if (!riscv_set_default_priv_spec (NULL)) + return; + } + + const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); if (error) { @@ -3504,26 +3564,66 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) demand_empty_rest_of_line (); } -/* Update arch attributes. */ +/* Update arch and priv attributes. If we don't set the corresponding ELF + attributes, then try to output the default ones. */ static void -riscv_write_out_arch_attr (void) +riscv_write_out_attrs (void) { - const char *arch_str = riscv_arch_str (xlen, &riscv_subsets); + const char *arch_str, *priv_str, *p; + /* versions[0] is major, versions[1] is minor, + and versions[3] is revision. */ + unsigned versions[3] = {0}, number = 0; + unsigned int i; + /* Re-write arch attribute to normalize the arch string. */ + arch_str = riscv_arch_str (xlen, &riscv_subsets); bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str); - xfree ((void *)arch_str); + + /* For the file without any instruction, we don't set the default_priv_spec + according to the priv attributes since the md_assemble isn't called. + Call riscv_set_default_priv_spec here for the above case, although + it seems strange. */ + if (!start_assemble + && !riscv_set_default_priv_spec (NULL)) + return; + + /* Re-write priv attributes by default_priv_spec. */ + priv_str = riscv_get_priv_spec_name (default_priv_spec); + p = priv_str; + for (i = 0; *p; ++p) + { + if (*p == '.' && i < 3) + { + versions[i++] = number; + number = 0; + } + else if (ISDIGIT (*p)) + number = (number * 10) + (*p - '0'); + else + { + as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str); + return; + } + } + versions[i] = number; + + /* Set the priv attributes. */ + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]); + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]); + bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]); } -/* Add the default contents for the .riscv.attributes section. */ +/* Add the default contents for the .riscv.attributes section. If any + ELF attribute or -march-attr options is set, call riscv_write_out_attrs + to update the arch and priv attributes. */ static void riscv_set_public_attributes (void) { - if (riscv_opts.arch_attr || explicit_arch_attr) - /* Re-write arch attribute to normalize the arch string. */ - riscv_write_out_arch_attr (); + if (riscv_opts.arch_attr || explicit_attr) + riscv_write_out_attrs (); } /* Called after all assembly has been done. */ @@ -3577,13 +3677,14 @@ static void s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) { int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); + unsigned old_xlen; + obj_attribute *attr; - if (tag == Tag_RISCV_arch) + explicit_attr = TRUE; + switch (tag) { - unsigned old_xlen = xlen; - - explicit_arch_attr = TRUE; - obj_attribute *attr; + case Tag_RISCV_arch: + old_xlen = xlen; attr = elf_known_obj_attributes_proc (stdoutput); if (!start_assemble) riscv_set_arch (attr[Tag_RISCV_arch].s); @@ -3599,6 +3700,17 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) as_warn (_("Could not set architecture and machine")); } + break; + + case Tag_RISCV_priv_spec: + case Tag_RISCV_priv_spec_minor: + case Tag_RISCV_priv_spec_revision: + if (start_assemble) + as_fatal (_(".attribute priv spec must set before any instructions")); + break; + + default: + break; } } diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d index 2e19e09..f027347 100644 --- a/gas/testsuite/gas/riscv/attribute-01.d +++ b/gas/testsuite/gas/riscv/attribute-01.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d index ae0195e..02b532d 100644 --- a/gas/testsuite/gas/riscv/attribute-02.d +++ b/gas/testsuite/gas/riscv/attribute-02.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d index 9916ff6..ded529a 100644 --- a/gas/testsuite/gas/riscv/attribute-03.d +++ b/gas/testsuite/gas/riscv/attribute-03.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d index 408464d..df6c818 100644 --- a/gas/testsuite/gas/riscv/attribute-04.d +++ b/gas/testsuite/gas/riscv/attribute-04.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d index ad24834..247f52e 100644 --- a/gas/testsuite/gas/riscv/attribute-05.d +++ b/gas/testsuite/gas/riscv/attribute-05.d @@ -7,5 +7,5 @@ File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" Tag_RISCV_unaligned_access: Unaligned access Tag_RISCV_priv_spec: 1 - Tag_RISCV_priv_spec_minor: 2 - Tag_RISCV_priv_spec_revision: 3 + Tag_RISCV_priv_spec_minor: 9 + Tag_RISCV_priv_spec_revision: 1 diff --git a/gas/testsuite/gas/riscv/attribute-05.s b/gas/testsuite/gas/riscv/attribute-05.s index 3b3b7f6..4920309 100644 --- a/gas/testsuite/gas/riscv/attribute-05.s +++ b/gas/testsuite/gas/riscv/attribute-05.s @@ -1,6 +1,6 @@ .attribute arch, "rv32g" .attribute priv_spec, 1 - .attribute priv_spec_minor, 2 - .attribute priv_spec_revision, 3 + .attribute priv_spec_minor, 9 + .attribute priv_spec_revision, 1 .attribute unaligned_access, 1 .attribute stack_align, 16 diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d index a2dd9fb..e1d62c4 100644 --- a/gas/testsuite/gas/riscv/attribute-06.d +++ b/gas/testsuite/gas/riscv/attribute-06.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d index 342a537..59f02b4 100644 --- a/gas/testsuite/gas/riscv/attribute-07.d +++ b/gas/testsuite/gas/riscv/attribute-07.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv64i2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d index c10ac0c..13b82a9 100644 --- a/gas/testsuite/gas/riscv/attribute-08.d +++ b/gas/testsuite/gas/riscv/attribute-08.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32e1p9" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d index cad1713..53945a2 100644 --- a/gas/testsuite/gas/riscv/attribute-09.d +++ b/gas/testsuite/gas/riscv/attribute-09.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d index ba903d1..91691fd 100644 --- a/gas/testsuite/gas/riscv/attribute-10.d +++ b/gas/testsuite/gas/riscv/attribute-10.d @@ -4,3 +4,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d index 667f21a..120e3de 100644 --- a/gas/testsuite/gas/riscv/attribute-unknown.d +++ b/gas/testsuite/gas/riscv/attribute-unknown.d @@ -4,5 +4,8 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... Tag_unknown_255: "test" Tag_unknown_256: 123 \(0x7b\) diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d index 8dc2a10..07cf05a 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d @@ -1,3 +1,11 @@ -#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 +#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p10.l +#readelf: -A + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 10 +#... diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d index 7d2406c..bf4b1db 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d @@ -1,3 +1,11 @@ -#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 +#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p11.l +#readelf: -A + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 11 +#... diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d index a2db291..c914334 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d @@ -1,3 +1,11 @@ -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9 +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p9.l +#readelf: -A + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 9 +#... diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d index e870cf5..e2c33d8 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d @@ -1,3 +1,12 @@ -#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 +#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p9p1.l +#readelf: -A + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 9 + Tag_RISCV_priv_spec_revision: 1 +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d index 5baaba4..032f964 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d @@ -7,3 +7,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d index a7d79a1..54a7621 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d @@ -7,3 +7,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d index d46dee8..67f0437 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d @@ -7,3 +7,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s index 1ad9500..0b7ffea 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s @@ -1,3 +1,3 @@ .attribute priv_spec, 1 - .attribute priv_spec_minor, 2 - .attribute priv_spec_revision, 3 + .attribute priv_spec_minor, 9 + .attribute priv_spec_revision, 1 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s index 1ad9500..0b7ffea 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s @@ -1,3 +1,3 @@ .attribute priv_spec, 1 - .attribute priv_spec_minor, 2 - .attribute priv_spec_revision, 3 + .attribute priv_spec_minor, 9 + .attribute priv_spec_revision, 1 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d index dc4c4e0..0aa6fe0 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec.d @@ -8,5 +8,5 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_priv_spec: 1 - Tag_RISCV_priv_spec_minor: 2 - Tag_RISCV_priv_spec_revision: 3 + Tag_RISCV_priv_spec_minor: 9 + Tag_RISCV_priv_spec_revision: 1 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d index 7a5bc81..5585fac 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d @@ -8,3 +8,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_stack_align: 16-bytes Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d index 1039930..91011a2 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d @@ -8,3 +8,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d index 12ca1c4..5bdea27 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d @@ -8,3 +8,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d index e41351d..ac886fb 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d @@ -8,3 +8,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d index ac2a766..dd45f76 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d @@ -7,3 +7,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d index 608c05e..ef0c154 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d @@ -8,3 +8,6 @@ Attribute Section: riscv File Attributes Tag_RISCV_arch: [a-zA-Z0-9_\"].* Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: [0-9_\"].* + Tag_RISCV_priv_spec_minor: [0-9_\"].* +#... -- 2.7.4