[PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options.

Nelson Chu
2020-05-06T02:56:02Z

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gas/
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.

opcodes/
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
---
gas/config/tc-riscv.c | 18 ++++++++++--------
gas/doc/c-riscv.texi | 16 ++++++++++++++++
opcodes/riscv-dis.c | 10 +++++++---
3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 6e30a06..b08339c 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3469,14 +3469,16 @@ md_show_usage (FILE *stream)
{
fprintf (stream, _("\
RISC-V options:\n\
- -fpic generate position-independent code\n\
- -fno-pic don't generate position-independent code (default)\n\
- -march=ISA set the RISC-V architecture\n\
- -mabi=ABI set the RISC-V ABI\n\
- -mrelax enable relax (default)\n\
- -mno-relax disable relax\n\
- -march-attr generate RISC-V arch attribute\n\
- -mno-arch-attr don't generate RISC-V arch attribute\n\
+ -fpic generate position-independent code\n\
+ -fno-pic don't generate position-independent code (default)\n\
+ -march=ISA set the RISC-V architecture\n\
+ -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
+ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
+ -mabi=ABI set the RISC-V ABI\n\
+ -mrelax enable relax (default)\n\
+ -mno-relax disable relax\n\
+ -march-attr generate RISC-V arch attribute\n\
+ -mno-arch-attr don't generate RISC-V arch attribute\n\
"));
}

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 488cf56..bf942c3 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -42,6 +42,22 @@ Don't generate position-independent code (default)
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.
+If this option and the architecture attributes aren’t set, then assembler
+will check the default configure setting --with-arch=ISA.
+
+@cindex @samp{-misa-spec=ISAspec} option, RISC-V
+@item -misa-spec=ISAspec
+Select the default isa spec version. If the version of ISA isn't set
+by -march, then assembler helps to set the version according to
+the default chosen spec. If this option isn't set, then assembler will
+check the default configure setting --with-isa-spec=ISAspec.
+
+@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
+@item -mpriv-spec=PRIVspec
+Select the privileged spec version. We can decide whether the CSR is valid or
+not according to the chosen spec. If this option and the privilege attributes
+aren't set, then assembler will check the default configure setting
+--with-priv-spec=PRIVspec.

@cindex @samp{-mabi=ABI} option, RISC-V
@item -mabi=ABI
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c5a0d36..f1f20c6 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -603,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));

fprintf (stream, _("\n\
- numeric Print numeric register names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));

fprintf (stream, _("\n\
- no-aliases Disassemble only into canonical instructions, rather\n\
- than into pseudoinstructions.\n"));
+ no-aliases Disassemble only into canonical instructions, rather\n\
+ than into pseudoinstructions.\n"));
+
+ fprintf (stream, _("\n\
+ priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
+ (1.9, 1.9.1, 1.10, 1.11).\n"));

fprintf (stream, _("\n"));
}
--
2.7.4