From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 8F1053896827 for ; Wed, 6 May 2020 02:56:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8F1053896827 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nelson.chu@sifive.com Received: by mail-pl1-x630.google.com with SMTP id u22so1662056plq.12 for ; Tue, 05 May 2020 19:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lpl1UwAPOpu5L8z8QvS4ac99t87uwkxLYinRO/99xu4=; b=KVSUw8gbM851Eb3IZ34xIk+i8tslGzWB/wGwYHev4oC6z7Zux+YDmv7TVL6zKYFJ7K fcETfhEt4cCeLJAOjy6sPXgc2tBjJSwUkbtiRxo4L3tzd3ZfnqJVhwXNVrsvkQcmncO3 iJKVE1Iny8DaTPxPjLKQLLIO+sKZGP3hvHEAracsjWN73l/lmn+3Nhvg8E/TidvPU4yH 8rFKjGya9oFnC7oeI5NEHBYGDCtozTI5sg5LK4bHcZxFC/lH/VGWfnykgAcKZVaC7jRD ADMmLxcfxr9b4YzAu4MrAJ2NFUGwbAEv5Ue1wnMZ2NqWMMIszq9FdSrz/OfXKMrtGtp6 TmOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lpl1UwAPOpu5L8z8QvS4ac99t87uwkxLYinRO/99xu4=; b=DCPse9VuZR+/Ts3s7DM3k3VF/NAsafl93G8IpmAXu0jtBcuvcFk4JM4ZK3W0E/ncw0 cI1R55HY+EbndOOXu5lm5faJMnDGkER0DMGYw0gdRVBn4/JOFkX20sQ84lSQMrVGsVS3 WBPq/lElUvxXQfJSUJUTi65CKPmLiErHiS51mckIgCJwd0dZ6T8IFFAS2LexpsIf2SSZ G37Z59c9pGOVH7OTDMGiDS5His3C6NXxvB+E7a6a4N9jf8UARdPdD6FdNVypEbzVugvv pvpjbcP7bO4e6XeRvEt+3+n2BEuGUDlGLEmM/TN63DkpOMfcB1Qp4OPbBWGvK364pDPA KS0g== X-Gm-Message-State: AGi0PuYDQ+J15bfwd/xrZK5AWV0G6ek/ko+jY/J5IthFb4OtfeRQCjgg mycVOeobqSn5QTxdUppCFGltpA== X-Google-Smtp-Source: APiQypI7lx2tAMpmnyv9/JxM5LDts/BCvov0XtA8lSq+Xw+358F0TAOrXH+WpNk3XctJPrE2rmlQ+Q== X-Received: by 2002:a17:902:361:: with SMTP id 88mr5759460pld.279.1588733761664; Tue, 05 May 2020 19:56:01 -0700 (PDT) Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id 141sm222996pfz.171.2020.05.05.19.56.00 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 May 2020 19:56:01 -0700 (PDT) From: Nelson Chu To: binutils@sourceware.org, gdb-patches@sourceware.org Cc: palmer@dabbelt.com, kito.cheng@sifive.com, jimw@sifive.com, andrew@sifive.com, andrew.burgess@embecosm.com, asb@lowrisc.org, maxim.blinov@embecosm.com, nelson.chu@sifive.com Subject: [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options. Date: Tue, 5 May 2020 19:55:47 -0700 Message-Id: <1588733747-18787-10-git-send-email-nelson.chu@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com> References: <1588733747-18787-1-git-send-email-nelson.chu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=yes Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 May 2020 02:56:04 -0000 gas/ * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise. opcodes/ * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. --- gas/config/tc-riscv.c | 18 ++++++++++-------- gas/doc/c-riscv.texi | 16 ++++++++++++++++ opcodes/riscv-dis.c | 10 +++++++--- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 6e30a06..b08339c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3469,14 +3469,16 @@ md_show_usage (FILE *stream) { fprintf (stream, _("\ RISC-V options:\n\ - -fpic generate position-independent code\n\ - -fno-pic don't generate position-independent code (default)\n\ - -march=ISA set the RISC-V architecture\n\ - -mabi=ABI set the RISC-V ABI\n\ - -mrelax enable relax (default)\n\ - -mno-relax disable relax\n\ - -march-attr generate RISC-V arch attribute\n\ - -mno-arch-attr don't generate RISC-V arch attribute\n\ + -fpic generate position-independent code\n\ + -fno-pic don't generate position-independent code (default)\n\ + -march=ISA set the RISC-V architecture\n\ + -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ + -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\ + -mabi=ABI set the RISC-V ABI\n\ + -mrelax enable relax (default)\n\ + -mno-relax disable relax\n\ + -march-attr generate RISC-V arch attribute\n\ + -mno-arch-attr don't generate RISC-V arch attribute\n\ ")); } diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 488cf56..bf942c3 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -42,6 +42,22 @@ Don't generate position-independent code (default) @cindex @samp{-march=ISA} option, RISC-V @item -march=ISA Select the base isa, as specified by ISA. For example -march=rv32ima. +If this option and the architecture attributes aren’t set, then assembler +will check the default configure setting --with-arch=ISA. + +@cindex @samp{-misa-spec=ISAspec} option, RISC-V +@item -misa-spec=ISAspec +Select the default isa spec version. If the version of ISA isn't set +by -march, then assembler helps to set the version according to +the default chosen spec. If this option isn't set, then assembler will +check the default configure setting --with-isa-spec=ISAspec. + +@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V +@item -mpriv-spec=PRIVspec +Select the privileged spec version. We can decide whether the CSR is valid or +not according to the chosen spec. If this option and the privilege attributes +aren't set, then assembler will check the default configure setting +--with-priv-spec=PRIVspec. @cindex @samp{-mabi=ABI} option, RISC-V @item -mabi=ABI diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c5a0d36..f1f20c6 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -603,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\n\ - numeric Print numeric register names, rather than ABI names.\n")); + numeric Print numeric register names, rather than ABI names.\n")); fprintf (stream, _("\n\ - no-aliases Disassemble only into canonical instructions, rather\n\ - than into pseudoinstructions.\n")); + no-aliases Disassemble only into canonical instructions, rather\n\ + than into pseudoinstructions.\n")); + + fprintf (stream, _("\n\ + priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\ + (1.9, 1.9.1, 1.10, 1.11).\n")); fprintf (stream, _("\n")); } -- 2.7.4