Re: [PATCH 3/4] gdb/aarch64: Display fp8 formats in registers

[Luis <luis.machado.foss@gmail.com>]

Hi Ezra,

Given Pedro's input about the representation of fp8's, I'm not sure this 
is the right path. Enabling these types for the registers would also 
make the types visible to the rest of GDB. And users can operate on them 
via arithmetic operators etc.

Being integers, the ending result wouldn´t be correct.

It might be viable to explore the python extension option to print the 
types accordingly. We already make vector fields (neon or sve) available 
as 8, 16, 32, 64 and 128 integers. Converting from that would therefore 
be easy.

Also, I'm not too keen on expanding even further these neon/sve union 
types. They are very hard to parse due to the multitude of 
representations. Ideally we´d put together some pseudo-registers to do 
the job. That would also help with remote debugging stub target 
description compatibility, as those wouldn´t need to expose these 
internal details of gdb.

Thoughts?

On 25/09/2025 22:18, Ezra.Sitorus@arm.com wrote:
> From: Ezra Sitorus <ezra.sitorus@arm.com>
> 
> Display fp8 formats for AArch64 vector/float registers. On a system
> without SVE, the V register and B-pseudo registers have the new
> e5m2/e4m3 formats. If it has SVE, then the Z registers, V and B pseudo
> registers get the new e5m2/e4m3 formats.
> ---
>   gdb/aarch64-tdep.c           | 41 ++++++++++++++++++++++++++++++++++++
>   gdb/aarch64-tdep.h           |  4 ++++
>   gdb/features/aarch64-fpu.c   | 10 +++++++++
>   gdb/features/aarch64-fpu.xml |  4 ++++
>   gdb/features/aarch64-sve.c   | 10 +++++++++
>   5 files changed, 69 insertions(+)
> 
> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
> index 500ac77d75a..8e71a75efbb 100644
> --- a/gdb/aarch64-tdep.c
> +++ b/gdb/aarch64-tdep.c
> @@ -2106,6 +2106,40 @@ aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
>     return sp & ~(CORE_ADDR) 15;
>   }
>   
> +/* Return the type for FP8 E5M2 format.  */
> +
> +static struct type *
> +aarch64_fp8_e5m2_type (struct gdbarch *gdbarch)
> +{
> +  aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
> +
> +  if (!tdep->fp8_e5m2_type)
> +    {
> +      type_allocator alloc (gdbarch);
> +      tdep->fp8_e5m2_type = init_float_type (
> +	  alloc, -1, "builtin_type_fp8_e5m2", floatformats_fp8_e5m2);
> +    }
> +
> +  return tdep->fp8_e5m2_type;
> +}
> +
> +/* Return the type for FP8 E4M3 format.  */
> +
> +static struct type *
> +aarch64_fp8_e4m3_type (struct gdbarch *gdbarch)
> +{
> +  aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch);
> +
> +  if (!tdep->fp8_e4m3_type)
> +    {
> +      type_allocator alloc (gdbarch);
> +      tdep->fp8_e4m3_type = init_float_type (
> +	  alloc, -1, "builtin_type_fp8_e4m3", floatformats_fp8_e4m3);
> +    }
> +
> +  return tdep->fp8_e4m3_type;
> +}
> +
>   /* Return the type for an AdvSISD Q register.  */
>   
>   static struct type *
> @@ -2247,6 +2281,9 @@ aarch64_vnb_type (struct gdbarch *gdbarch)
>         elem = builtin_type (gdbarch)->builtin_int8;
>         append_composite_type_field (t, "s", elem);
>   
> +      append_composite_type_field (t, "e5m2", aarch64_fp8_e5m2_type (gdbarch));
> +      append_composite_type_field (t, "e4m3", aarch64_fp8_e4m3_type (gdbarch));
> +
>         tdep->vnb_type = t;
>       }
>   
> @@ -2516,6 +2553,10 @@ aarch64_vnv_type (struct gdbarch *gdbarch)
>   				   init_vector_type (bt->builtin_uint8, 16));
>         append_composite_type_field (sub, "s",
>   				   init_vector_type (bt->builtin_int8, 16));
> +      append_composite_type_field (sub, "e5m2",
> +				   init_vector_type (aarch64_fp8_e5m2_type (gdbarch), 16));
> +      append_composite_type_field (sub, "e4m3",
> +				   init_vector_type (aarch64_fp8_e4m3_type (gdbarch), 16));
>         append_composite_type_field (t, "b", sub);
>   
>         sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
> diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
> index 99e7d26ce4a..d9f44f1c15c 100644
> --- a/gdb/aarch64-tdep.h
> +++ b/gdb/aarch64-tdep.h
> @@ -93,6 +93,10 @@ struct aarch64_gdbarch_tdep : gdbarch_tdep_base
>     struct type *sme_tile_slice_type_h = nullptr;
>     struct type *sme_tile_slice_type_b = nullptr;
>   
> +  /* Types for FP8 formats.  */
> +  struct type *fp8_e5m2_type = nullptr;
> +  struct type *fp8_e4m3_type = nullptr;
> +
>     /* Vector of names for SME pseudo-registers.  The number of elements is
>        different for each distinct svl value.  */
>     std::vector<std::string> sme_pseudo_names;
> diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
> index 27e75524cfe..13825c74640 100644
> --- a/gdb/features/aarch64-fpu.c
> +++ b/gdb/features/aarch64-fpu.c
> @@ -46,6 +46,12 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
>     element_type = tdesc_named_type (feature, "int8");
>     tdesc_create_vector (feature, "v16i", element_type, 16);
>   
> +  element_type = tdesc_named_type (feature, "fp8_e5m2");
> +  tdesc_create_vector (feature, "v16fp8e5m2", element_type, 16);
> +
> +  element_type = tdesc_named_type (feature, "fp8_e4m3");
> +  tdesc_create_vector (feature, "v16fp8e4m3", element_type, 16);
> +
>     element_type = tdesc_named_type (feature, "uint128");
>     tdesc_create_vector (feature, "v1u", element_type, 1);
>   
> @@ -85,6 +91,10 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
>     tdesc_add_field (type_with_fields, "u", field_type);
>     field_type = tdesc_named_type (feature, "v16i");
>     tdesc_add_field (type_with_fields, "s", field_type);
> +  field_type = tdesc_named_type (feature, "v16fp8e5m2");
> +  tdesc_add_field (type_with_fields, "e5m2", field_type);
> +  field_type = tdesc_named_type (feature, "v16fp8e4m3");
> +  tdesc_add_field (type_with_fields, "e4m3", field_type);
>   
>     type_with_fields = tdesc_create_union (feature, "vnq");
>     field_type = tdesc_named_type (feature, "v1u");
> diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
> index 509824f55fb..26e292ee625 100644
> --- a/gdb/features/aarch64-fpu.xml
> +++ b/gdb/features/aarch64-fpu.xml
> @@ -20,6 +20,8 @@
>     <vector id="v8bf16" type="bfloat16" count="8"/>
>     <vector id="v16u" type="uint8" count="16"/>
>     <vector id="v16i" type="int8" count="16"/>
> +  <vector id="v16fp8e5m2" type="fp8_e5m2" count="16"/>
> +  <vector id="v16fp8e4m3" type="fp8_e4m3" count="16"/>
>     <vector id="v1u" type="uint128" count="1"/>
>     <vector id="v1i" type="int128" count="1"/>
>     <union id="vnd">
> @@ -41,6 +43,8 @@
>     <union id="vnb">
>       <field name="u" type="v16u"/>
>       <field name="s" type="v16i"/>
> +    <field name="e5m2" type="v16fp8e5m2"/>
> +    <field name="e4m3" type="v16fp8e4m3"/>
>     </union>
>     <union id="vnq">
>       <field name="u" type="v1u"/>
> diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
> index 0b15881f073..24b88c32fc1 100644
> --- a/gdb/features/aarch64-sve.c
> +++ b/gdb/features/aarch64-sve.c
> @@ -70,6 +70,12 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
>     element_type = tdesc_named_type (feature, "int8");
>     tdesc_create_vector (feature, "svevbs", element_type, 16 * scale);
>   
> +  element_type = tdesc_named_type (feature, "fp8_e5m2");
> +  tdesc_create_vector (feature, "svevbfp8e5m2", element_type, 16 * scale);
> +
> +  element_type = tdesc_named_type (feature, "fp8_e4m3");
> +  tdesc_create_vector (feature, "svevbfp8e4m3", element_type, 16 * scale);
> +
>     type_with_fields = tdesc_create_union (feature, "svevnq");
>     field_type = tdesc_named_type (feature, "svevqu");
>     tdesc_add_field (type_with_fields, "u", field_type);
> @@ -105,6 +111,10 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
>     tdesc_add_field (type_with_fields, "u", field_type);
>     field_type = tdesc_named_type (feature, "svevbs");
>     tdesc_add_field (type_with_fields, "s", field_type);
> +  field_type = tdesc_named_type (feature, "svevbfp8e5m2");
> +  tdesc_add_field (type_with_fields, "e5m2", field_type);
> +  field_type = tdesc_named_type (feature, "svevbfp8e4m3");
> +  tdesc_add_field (type_with_fields, "e4m3", field_type);
>   
>     type_with_fields = tdesc_create_union (feature, "svev");
>     field_type = tdesc_named_type (feature, "svevnq");