From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102180 invoked by alias); 1 Dec 2016 13:39:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 102110 invoked by uid 89); 1 Dec 2016 13:39:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Extended, HTo:D*nl, 2007-2016, 20072016 X-HELO: mga05.intel.com Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Dec 2016 13:39:18 +0000 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 01 Dec 2016 05:39:16 -0800 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga004.jf.intel.com with ESMTP; 01 Dec 2016 05:39:15 -0800 Received: from ulvlx001.iul.intel.com (ulvlx001.iul.intel.com [172.28.207.17]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id uB1DdEuJ029902; Thu, 1 Dec 2016 13:39:14 GMT Received: from ulvlx001.iul.intel.com (localhost [127.0.0.1]) by ulvlx001.iul.intel.com with ESMTP id uB1DdEC8030856; Thu, 1 Dec 2016 14:39:14 +0100 Received: (from msturm@localhost) by ulvlx001.iul.intel.com with œ id uB1DdEvK030853; Thu, 1 Dec 2016 14:39:14 +0100 From: Michael Sturm To: mark.kettenis@xs4all.nl, palves@redhat.com, eliz@gnu.org Cc: gdb-patches@sourceware.org, michael.sturm@intel.com Subject: [PATCH v2 1/5] Sync up x86-gcc-cpuid.h with cpuid.h from gcc-6 branch. Date: Thu, 01 Dec 2016 13:39:00 -0000 Message-Id: <1480599538-30543-2-git-send-email-michael.sturm@intel.com> In-Reply-To: <1480599538-30543-1-git-send-email-michael.sturm@intel.com> References: <1480599538-30543-1-git-send-email-michael.sturm@intel.com> X-SW-Source: 2016-12/txt/msg00033.txt.bz2 Pedro suggested a separate patch synching with GCCs cpuid.h instead of just adding new bits for PKU feature. gdb/Changelog: 2016-11-14 Michael Sturm * nat/x86-gcc-cpuid.h: Replace with copy of cpuid.h from gcc-6 branch. Change-Id: I7fadd372db689907475779c12400d123d40a71ce Signed-off-by: Michael Sturm --- gdb/nat/x86-gcc-cpuid.h | 128 ++++++++++++++++++------------------------------ 1 file changed, 48 insertions(+), 80 deletions(-) diff --git a/gdb/nat/x86-gcc-cpuid.h b/gdb/nat/x86-gcc-cpuid.h index 1045521..5d81b23 100644 --- a/gdb/nat/x86-gcc-cpuid.h +++ b/gdb/nat/x86-gcc-cpuid.h @@ -1,29 +1,7 @@ /* - * Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not + * Helper cpuid.h file copied from gcc-6. Code in gdb should not * include this directly, but pull in x86-cpuid.h and use that func. */ -/* - * Copyright (C) 2007-2016 Free Software Foundation, Inc. - * - * This file is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 3, or (at your option) any - * later version. - * - * This file is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * Under Section 7 of GPL version 3, you are granted additional - * permissions described in the GCC Runtime Library Exception, version - * 3.1, as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License and - * a copy of the GCC Runtime Library Exception along with this program; - * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - * . - */ /* %ecx */ #define bit_SSE3 (1 << 0) @@ -61,6 +39,7 @@ #define bit_LWP (1 << 15) #define bit_FMA4 (1 << 16) #define bit_TBM (1 << 21) +#define bit_MWAITX (1 << 29) /* %edx */ #define bit_MMXEXT (1 << 22) @@ -68,24 +47,46 @@ #define bit_3DNOWP (1 << 30) #define bit_3DNOW (1 << 31) +/* %ebx. */ +#define bit_CLZERO (1 << 0) + /* Extended Features (%eax == 7) */ +/* %ebx */ #define bit_FSGSBASE (1 << 0) #define bit_BMI (1 << 3) #define bit_HLE (1 << 4) #define bit_AVX2 (1 << 5) #define bit_BMI2 (1 << 8) #define bit_RTM (1 << 11) +#define bit_MPX (1 << 14) #define bit_AVX512F (1 << 16) -#define bit_MPX (1 << 14) +#define bit_AVX512DQ (1 << 17) #define bit_RDSEED (1 << 18) #define bit_ADX (1 << 19) +#define bit_AVX512IFMA (1 << 21) +#define bit_CLFLUSHOPT (1 << 23) +#define bit_CLWB (1 << 24) #define bit_AVX512PF (1 << 26) #define bit_AVX512ER (1 << 27) #define bit_AVX512CD (1 << 28) #define bit_SHA (1 << 29) +#define bit_AVX512BW (1 << 30) +#define bit_AVX512VL (1 << 31) + +/* %ecx */ +#define bit_PREFETCHWT1 (1 << 0) +#define bit_AVX512VBMI (1 << 1) +#define bit_PKU (1 << 3) +#define bit_OSPKE (1 << 4) + +/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ +#define bit_BNDREGS (1 << 3) +#define bit_BNDCSR (1 << 4) /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ #define bit_XSAVEOPT (1 << 0) +#define bit_XSAVEC (1 << 1) +#define bit_XSAVES (1 << 3) /* Signatures for different CPU implementations as returned in uses of cpuid with level 0. */ @@ -141,55 +142,6 @@ #define signature_VORTEX_ecx 0x436f5320 #define signature_VORTEX_edx 0x36387865 -#if defined(__i386__) && defined(__PIC__) -/* %ebx may be the PIC register. */ -#if __GNUC__ >= 3 -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#else -/* Host GCCs older than 3.0 weren't supporting Intel asm syntax - nor alternatives in i386 code. */ -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchgl\t%%ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchgl\t%%ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#endif -#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__) -/* %rbx may be the PIC register. */ -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ - "cpuid\n\t" \ - "xchg{q}\t{%%}rbx, %q1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ - "cpuid\n\t" \ - "xchg{q}\t{%%}rbx, %q1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#else #define __cpuid(level, a, b, c, d) \ __asm__ ("cpuid\n\t" \ : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ @@ -199,7 +151,7 @@ __asm__ ("cpuid\n\t" \ : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ : "0" (level), "2" (count)) -#endif + /* Return highest supported input value for cpuid instruction. ext can be either 0x0 or 0x8000000 to return highest supported value for @@ -258,21 +210,37 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig) return __eax; } -/* Return cpuid data for requested cpuid level, as found in returned +/* Return cpuid data for requested cpuid leaf, as found in returned eax, ebx, ecx and edx registers. The function checks if cpuid is supported and returns 1 for valid cpuid information or 0 for - unsupported cpuid level. All pointers are required to be non-null. */ + unsupported cpuid leaf. All pointers are required to be non-null. */ static __inline int -__get_cpuid (unsigned int __level, +__get_cpuid (unsigned int __leaf, unsigned int *__eax, unsigned int *__ebx, unsigned int *__ecx, unsigned int *__edx) { - unsigned int __ext = __level & 0x80000000; + unsigned int __ext = __leaf & 0x80000000; + + if (__get_cpuid_max (__ext, 0) < __leaf) + return 0; + + __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx); + return 1; +} + +/* Same as above, but sub-leaf can be specified. */ + +static __inline int +__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + unsigned int __ext = __leaf & 0x80000000; - if (__get_cpuid_max (__ext, 0) < __level) + if (__get_cpuid_max (__ext, 0) < __leaf) return 0; - __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); + __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx); return 1; } -- 1.8.4.2