[PATCH 1/3] gdb.trace: Move more target dependencies to trace-support.exp

Marcin Kościelnicki
2016-02-20T14:02:19Z

While groveling through the old PPC64 tracepoint support patch, I've
noticed a few target dependencies in the testsuite that both me and
Antoine missed for s390 and ARM tracepoints, respectively. This patch
moves them all to one place, so that anyone working on a new target
will hopefully see the whole set of needed changes.

For some strange reason, the call_insn setting code already knew about
powerpc, s390, and mips - I went ahead and added the remaining
information about those. I'm not particularly sure if I got mips right,
but that won't matter anyway until someone actually writes tracepoint
support for that.

Tested on x86_64, i386, ppc, ppc64, ppc64le, s390, s390x. Would be good
to test it on aarch64.

gdb/testsuite/ChangeLog:

* gdb.trace/entry-values.exp: Move call_insn setting to
trace-support.exp.
* gdb.trace/ftrace.exp: Move arg0exp setting to trace-support.exp.
* gdb.trace/mi-trace-unavailable.exp (proc_trace_unavailable): Move
pcnum setting to trace-support.exp, change fixed register 0 to
gpr0num variable.
* lib/trace-support.exp: Add setting pcnum, gpr0num, arg0exp,
call_insn; add powerpc, s390, and mips support.
---
Split up and removed arm in this version.

gdb/testsuite/ChangeLog | 11 ++++
gdb/testsuite/gdb.trace/entry-values.exp | 26 +--------
gdb/testsuite/gdb.trace/ftrace.exp | 11 ----
gdb/testsuite/gdb.trace/mi-trace-unavailable.exp | 25 +++------
gdb/testsuite/lib/trace-support.exp | 69 +++++++++++++++++++++++-
5 files changed, 87 insertions(+), 55 deletions(-)

diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog
index 5676cac..ec2773b 100644
--- a/gdb/testsuite/ChangeLog
+++ b/gdb/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2016-02-19 Marcin KoÅ›cielnicki <koriakin@0x04.net>
+
+ * gdb.trace/entry-values.exp: Move call_insn setting to
+ trace-support.exp.
+ * gdb.trace/ftrace.exp: Move arg0exp setting to trace-support.exp.
+ * gdb.trace/mi-trace-unavailable.exp (proc_trace_unavailable): Move
+ pcnum setting to trace-support.exp, change fixed register 0 to
+ gpr0num variable.
+ * lib/trace-support.exp: Add setting pcnum, gpr0num, arg0exp,
+ call_insn; add powerpc, s390, and mips support.
+
2016-02-18 Iain Buclaw <ibuclaw@gdcproject.org>

* lib/future.exp: Add D support.
diff --git a/gdb/testsuite/gdb.trace/entry-values.exp b/gdb/testsuite/gdb.trace/entry-values.exp
index 825928d..75c788a 100644
--- a/gdb/testsuite/gdb.trace/entry-values.exp
+++ b/gdb/testsuite/gdb.trace/entry-values.exp
@@ -12,6 +12,8 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+load_lib "trace-support.exp"
load_lib dwarf.exp

# This test can only be run on targets which support DWARF-2 and use gas.
@@ -37,30 +39,6 @@ gdb_load ${binfile}1.o

set returned_from_foo ""

-if { [istarget "arm*-*-*"] || [istarget "aarch64*-*-*"] } {
- set call_insn "bl"
-} elseif { [istarget "s390*-*-*"] } {
- set call_insn "brasl"
-} elseif { [istarget "powerpc*-*-*"] } {
- set call_insn "bl"
-} elseif { [istarget "mips*-*-*"] } {
- # Skip the delay slot after the instruction used to make a call
- # (which can be a jump or a branch) if it has one.
- #
- # JUMP (or BRANCH) foo
- # insn1
- # insn2
- #
- # Most MIPS instructions used to make calls have a delay slot.
- # These include JAL, JALS, JALX, JALR, JALRS, BAL and BALS.
- # In this case the program continues from `insn2' when `foo'
- # returns. The only exception is JALRC, in which case execution
- # resumes from `insn1' instead.
- set call_insn {jalrc|[jb]al[sxr]*[ \t][^\r\n]+\r\n}
-} else {
- set call_insn "call"
-}
-
# Calculate the offset of the instruction in bar returned from foo.
set test "disassemble bar"
gdb_test_multiple $test $test {
diff --git a/gdb/testsuite/gdb.trace/ftrace.exp b/gdb/testsuite/gdb.trace/ftrace.exp
index 15ad7e7..b9b2d8b 100644
--- a/gdb/testsuite/gdb.trace/ftrace.exp
+++ b/gdb/testsuite/gdb.trace/ftrace.exp
@@ -239,17 +239,6 @@ test_ftrace_condition "(globvar >> 2) == 2" "globvar" { 8 9 10 }
# Test emit_call by accessing trace state variables.
test_ftrace_condition "(\$tsv = \$tsv + 2) > 10" "globvar" { 6 7 8 9 10 }

-# This expression is used for testing emit_reg.
-if [is_amd64_regs_target] {
- set arg0exp "\$rdi"
-} elseif [is_x86_like_target] {
- set arg0exp "*(int *) (\$ebp + 8)"
-} elseif { [istarget "aarch64*-*-*"] } {
- set arg0exp "\$x0"
-} else {
- set arg0exp ""
-}
-
if { "$arg0exp" != "" } {
test_ftrace_condition "($arg0exp > 500)" "globvar" { 6 7 8 9 10 }
}
diff --git a/gdb/testsuite/gdb.trace/mi-trace-unavailable.exp b/gdb/testsuite/gdb.trace/mi-trace-unavailable.exp
index 82c6101..a39b82e 100644
--- a/gdb/testsuite/gdb.trace/mi-trace-unavailable.exp
+++ b/gdb/testsuite/gdb.trace/mi-trace-unavailable.exp
@@ -77,6 +77,8 @@ mi_gdb_test "-trace-save -ctf ${tracefile}.ctf" ".*\\^done" \

proc test_trace_unavailable { data_source } {
global decimal
+ global pcnum
+ global gpr0num

with_test_prefix "$data_source" {

@@ -130,28 +132,15 @@ proc test_trace_unavailable { data_source } {
".*\\^done,found=\"1\",tracepoint=\"${decimal}\",traceframe=\"1\",frame=\{.*" \
"-trace-find frame-number 1"

- set pcnum 0
- if [is_amd64_regs_target] {
- set pcnum 16
- } elseif [is_x86_like_target] {
- set pcnum 8
- } elseif [is_aarch64_target] {
- set pcnum 32
- } else {
- # Other ports support tracepoint should define the number
- # of its own pc register.
- }
-
- if { $pcnum != 0 } {
+ if { $pcnum != -1 } {
global hex
- # Test that register 0 and PC are displayed, and register
- # 0 is unavailable.
- mi_gdb_test "-data-list-register-values x 0 ${pcnum}" \
- ".*\\^done,register-values=\\\[\{number=\"0\",value=\"<unavailable>\"\},\{number=\"${pcnum}\",value=\"${hex}\"\}\\\]" \
+ # Test that GPR0 and PC are displayed, and GPR0 is unavailable.
+ mi_gdb_test "-data-list-register-values x ${gpr0num} ${pcnum}" \
+ ".*\\^done,register-values=\\\[\{number=\"${gpr0num}\",value=\"<unavailable>\"\},\{number=\"${pcnum}\",value=\"${hex}\"\}\\\]" \
"-data-list-register-values x"

# Test that only available register PC is displayed.
- mi_gdb_test "-data-list-register-values --skip-unavailable x 0 ${pcnum}" \
+ mi_gdb_test "-data-list-register-values --skip-unavailable x ${gpr0num} ${pcnum}" \
".*\\^done,register-values=\\\[\{number=\"${pcnum}\",value=\"${hex}\"\}\\\]" \
"-data-list-register-values --skip-unavailable x"
}
diff --git a/gdb/testsuite/lib/trace-support.exp b/gdb/testsuite/lib/trace-support.exp
index f593c43..0565030 100644
--- a/gdb/testsuite/lib/trace-support.exp
+++ b/gdb/testsuite/lib/trace-support.exp
@@ -20,26 +20,91 @@

#
-# Program counter / stack pointer / frame pointer for supported targets.
-# Used in many tests, kept here to avoid duplication.
+# Target-specific information. Used in many tests, kept here
+# to avoid duplication and make it easier to add a new target.
#

if [is_amd64_regs_target] {
+ # Frame pointer.
set fpreg "rbp"
+ # Stack pointer.
set spreg "rsp"
+ # Program counter.
set pcreg "rip"
+ # How to collect the first argument to a function. Used to test
+ # register usage in tracepoint conditions.
+ set arg0exp "\$rdi"
+ # The mnemonic of the usual, unconditional call instruction.
+ set call_insn "call"
+ # Number of the PC register.
+ set pcnum 16
+ # Number of any GPR (it's supposed to be some register that's not
+ # collected by default).
+ set gpr0num 0
} elseif [is_x86_like_target] {
set fpreg "ebp"
set spreg "esp"
set pcreg "eip"
+ set arg0exp "*(int *) (\$ebp + 8)"
+ set call_insn "call"
+ set pcnum 8
+ set gpr0num 0
} elseif [is_aarch64_target] {
set fpreg "x29"
set spreg "sp"
set pcreg "pc"
+ set arg0exp "\$x0"
+ set call_insn "bl"
+ set pcnum 32
+ set gpr0num 0
+} elseif [istarget "powerpc*-*-*"] {
+ set fpreg "r31"
+ set spreg "r1"
+ set pcreg "pc"
+ set arg0exp "\$r3"
+ set call_insn "bl"
+ set pcnum 64
+ set gpr0num 0
+} elseif [istarget "s390*-*-*"] {
+ set fpreg "r11"
+ set spreg "r15"
+ set pcreg "pc"
+ set arg0exp "\$r2"
+ set call_insn "brasl"
+ # Strictly speaking, this is PSWA, not PC.
+ set pcnum 1
+ set gpr0num 2
+} elseif { [istarget "mips*-*-*"] } {
+ set fpreg "s8"
+ set spreg "sp"
+ set pcreg "pc"
+ set arg0exp "\$a0"
+ # Skip the delay slot after the instruction used to make a call
+ # (which can be a jump or a branch) if it has one.
+ #
+ # JUMP (or BRANCH) foo
+ # insn1
+ # insn2
+ #
+ # Most MIPS instructions used to make calls have a delay slot.
+ # These include JAL, JALS, JALX, JALR, JALRS, BAL and BALS.
+ # In this case the program continues from `insn2' when `foo'
+ # returns. The only exception is JALRC, in which case execution
+ # resumes from `insn1' instead.
+ set call_insn {jalrc|[jb]al[sxr]*[ \t][^\r\n]+\r\n}
+ set pcnum 37
+ set gpr0num 0
} else {
+ # Defaults. Probably won't work, but we don't want to error out
+ # here on unsupported platforms, since this file is imported to check
+ # for supported platforms in the first place.
set fpreg "fp"
set spreg "sp"
set pcreg "pc"
+ set arg0exp "\$a0"
+ set call_insn "call"
+ set pcnum -1
+ set gpr0num -1
}

#
--
2.7.1