From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 58014 invoked by alias); 2 Nov 2015 19:11:32 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 58002 invoked by uid 89); 2 Nov 2015 19:11:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: xyzzy.0x04.net Received: from xyzzy.0x04.net (HELO xyzzy.0x04.net) (109.74.193.254) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 02 Nov 2015 19:11:29 +0000 Received: from hogfather.0x04.net (89-65-84-110.dynamic.chello.pl [89.65.84.110]) by xyzzy.0x04.net (Postfix) with ESMTPS id 5CFF03FEE2; Mon, 2 Nov 2015 20:11:45 +0100 (CET) Received: by hogfather.0x04.net (Postfix, from userid 1000) id 90C355800D4; Mon, 2 Nov 2015 20:11:27 +0100 (CET) From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= To: uweigand@de.ibm.com Cc: gdb-patches@sourceware.org Subject: Re: [RFC][PATCH][PR 18376] gdb: Add process record and replay support for s390. Date: Mon, 02 Nov 2015 19:11:00 -0000 Message-Id: <1446491482-3703-1-git-send-email-koriakin@0x04.net> In-Reply-To: <20151030103938.99AE45C3D@oc7340732750.ibm.com> References: <20151030103938.99AE45C3D@oc7340732750.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-SW-Source: 2015-11/txt/msg00023.txt.bz2 Here comes v2. I have added pseudo-support for TBEGIN (just to let it abort and fallback), as well as PPA and ETND (on the off-chance someone uses them). I have also found three missing break statements and fixed those. The second patch implements single-stepping over a MVCLE+JO pair (as well as other partial-execution instructions that can write memory). I haven't limitted it to record-only - AFAICT it doesn't cause any problems without record (in fact, it should decrease context switches for large transfers), but I'll restrict that if necessary. As for the Uniersity of Syracuse machines, I do have access, and they are only z196. There's also an ambiguity in LCBB opcode documentation: it produces a 32-bit unsigned result, but the text mentions storing it to the general register (not to bits 32-63 of a general register, as is common for documentation of proper 32-bit opcodes). I don't have a vector-supporting machine, so I can't check what is correct. The patch goes the safe way and assumes all 64 bits of GR can be changed.