[PATCH] MIPS: Handle the DSP registers for bare metal

[Yao Qi <yao@codesourcery.com>]

In 2007, Maciej submitted the patch handling DSP registers on both
linux and bare metal targets.

  MIPS: Handle the DSP registers
  https://sourceware.org/ml/gdb-patches/2007-12/msg00150.html

the patch was reviewed but didn't go in.  Then Maciej resubmit the
patch again only for the linux target, which was committed.

  [PATCH] MIPS/Linux: DSP ASE support
  https://sourceware.org/ml/gdb-patches/2011-11/msg00586.html

This patch is about the left over of handling DSP registers.  Since
the offset and layout of DSP registers vary between and linux and bare
metal, this patch is to adjust the offset for these registers.

gdb:

2014-12-18  Maciej W. Rozycki  <macro@codesourcery.com>
	    Chris Dearman  <chris@mips.com>

	* mips-tdep.c (NUM_MIPS_PROCESSOR_REGS): Set from
	MIPS_LAST_EMBED_REGNUM.
	(mips_gdbarch_init): Add embedded DSP support.
	* mips-tdep.h (MIPS_EMBED_CP2_REGNUM): Offset to CP2 registers.
	(MIPS_EMBED_DSPACC_REGNUM): Offset to DSP accumulator registers.
	(MIPS_EMBED_DSPCTL_REGNUM): Offset to DSP control registers.
	(MIPS_LAST_EMBED_REGNUM): Update accordingly.
	(MIPS_EMBED_NUM_REGS): New value to make sure that an even
	number of registers is used.
---
 gdb/mips-tdep.c | 15 ++++++++++-----
 gdb/mips-tdep.h | 23 ++++++++++++++++++++---
 2 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 60f43ac..1fdb216 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -546,7 +546,7 @@ static struct cmd_list_element *showmipscmdlist = NULL;
    are listed in the following tables.  */
 
 enum
-{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
+{ NUM_MIPS_PROCESSOR_REGS = (MIPS_LAST_EMBED_REGNUM + 1 - 32) };
 
 /* Generic MIPS.  */
 
@@ -8191,7 +8191,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   struct gdbarch_tdep *tdep;
   int elf_flags;
   enum mips_abi mips_abi, found_abi, wanted_abi;
-  int i, num_regs;
+  int i, num_regs, dsp_space;
   enum mips_fpu_type fpu_type;
   struct tdesc_arch_data *tdesc_data = NULL;
   int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY;
@@ -8214,6 +8214,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
       mips_regnum.fp_implementation_revision = 70;
       mips_regnum.dspacc = dspacc = -1;
       mips_regnum.dspctl = dspctl = -1;
+      dsp_space = 0;
       num_regs = 71;
       reg_names = mips_irix_reg_names;
     }
@@ -8231,6 +8232,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
       mips_regnum.dspctl = -1;
       dspacc = 72;
       dspctl = 78;
+      dsp_space = 0;
       num_regs = 79;
       reg_names = mips_linux_reg_names;
     }
@@ -8244,8 +8246,9 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
       mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
       mips_regnum.fp_control_status = 70;
       mips_regnum.fp_implementation_revision = 71;
-      mips_regnum.dspacc = dspacc = -1;
-      mips_regnum.dspctl = dspctl = -1;
+      mips_regnum.dspacc = dspacc = MIPS_EMBED_DSPACC_REGNUM;
+      mips_regnum.dspctl = dspctl = MIPS_EMBED_DSPCTL_REGNUM;
+      dsp_space = 1;
       num_regs = MIPS_LAST_EMBED_REGNUM + 1;
       if (info.bfd_arch_info != NULL
           && info.bfd_arch_info->mach == bfd_mach_mips3900)
@@ -8357,16 +8360,18 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 	  /* The DSP registers are optional; it's OK if they are absent.  */
 	  if (feature != NULL)
 	    {
-	      i = 0;
+	      i = dsp_space;
 	      valid_p = 1;
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
 						  dspacc + i++, "hi1");
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
 						  dspacc + i++, "lo1");
+	      i += dsp_space;
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
 						  dspacc + i++, "hi2");
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
 						  dspacc + i++, "lo2");
+	      i += dsp_space;
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
 						  dspacc + i++, "hi3");
 	      valid_p &= tdesc_numbered_register (feature, tdesc_data,
diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h
index 186f158..f781245 100644
--- a/gdb/mips-tdep.h
+++ b/gdb/mips-tdep.h
@@ -139,9 +139,26 @@ enum
   MIPS_EMBED_PC_REGNUM = 37,
   MIPS_EMBED_FP0_REGNUM = 38,
   MIPS_UNUSED_REGNUM = 73,	/* Never used, FIXME.  */
-  MIPS_FIRST_EMBED_REGNUM = 74,	/* First CP0 register for embedded use.  */
-  MIPS_PRID_REGNUM = 89,	/* Processor ID.  */
-  MIPS_LAST_EMBED_REGNUM = 89	/* Last one.  */
+  MIPS_FIRST_EMBED_REGNUM = 74,	/* First CP register for embedded use.  */
+  MIPS_EMBED_CP0_REGNUM = MIPS_FIRST_EMBED_REGNUM,
+				/* CP0 data registers: 8 banks of 32.  */
+  MIPS_PRID_REGNUM = (MIPS_EMBED_CP0_REGNUM + 15),
+				/* Processor ID.  */
+  MIPS_EMBED_CP2_REGNUM = (MIPS_EMBED_CP0_REGNUM + 8 * 32),
+				/* CP2 data registers: 8 banks of 32.  */
+  MIPS_EMBED_CP2CTL_REGNUM = (MIPS_EMBED_CP2_REGNUM + 8 * 32),
+				/* CP2 control registers: 32.  */
+  MIPS_EMBED_DSPACC_REGNUM = (MIPS_EMBED_CP2CTL_REGNUM + 32),
+				/* DSP/SmartMIPS registers:
+				   ACX, Hi1, Lo1, ACX1,
+				   Hi2, Lo2, ACX2, Hi3, Lo3, ACX3.  */
+  MIPS_EMBED_DSPCTL_REGNUM = (MIPS_EMBED_DSPACC_REGNUM + 10),
+				/* DSP DSPCTL0..1 registers.  */
+  MIPS_EMBED_NUM_REGS = (MIPS_EMBED_DSPCTL_REGNUM + 2),
+				/* Total number of actual registers.  */
+  MIPS_LAST_EMBED_REGNUM
+    = ((MIPS_EMBED_NUM_REGS + MIPS_EMBED_NUM_REGS % 2) - 1)
+				/* Last one, including padding to even.  */
 };
 
 /* Defined in mips-tdep.c and used in remote-mips.c.  */
-- 
1.9.3