From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11049 invoked by alias); 23 Apr 2014 13:03:18 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 11040 invoked by uid 89); 23 Apr 2014 13:03:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mga11.intel.com Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Apr 2014 13:03:16 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 23 Apr 2014 06:03:13 -0700 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 23 Apr 2014 06:02:49 -0700 Received: from ulvlx001.iul.intel.com (ulvlx001.iul.intel.com [172.28.207.17]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id s3ND2nBk003531; Wed, 23 Apr 2014 14:02:49 +0100 Received: from ulvlx001.iul.intel.com (localhost [127.0.0.1]) by ulvlx001.iul.intel.com with ESMTP id s3ND2mkI009364; Wed, 23 Apr 2014 15:02:48 +0200 Received: (from msturm@localhost) by ulvlx001.iul.intel.com with œ id s3ND2mGO009360; Wed, 23 Apr 2014 15:02:48 +0200 From: Michael Sturm To: palves@redhat.com, eliz@gnu.org, mark.kettenis@xs4all.nl, walfred.tedeschi@intel.com Cc: gdb-patches@sourceware.org, Michael Sturm Subject: [PATCH V5 3/3] Add AVX512 feature description to GDB manual Date: Wed, 23 Apr 2014 13:03:00 -0000 Message-Id: <1398258160-9070-4-git-send-email-michael.sturm@intel.com> In-Reply-To: <1398258160-9070-1-git-send-email-michael.sturm@intel.com> References: <1398258160-9070-1-git-send-email-michael.sturm@intel.com> X-SW-Source: 2014-04/txt/msg00440.txt.bz2 2013-09-11 Michael Sturm Walfred Tedeschi * NEWS: Add note about new support for AVX512. doc/ * gdb.texinfo (i386 Features): Add description of AVX512 registers. --- gdb/NEWS | 5 +++++ gdb/doc/gdb.texinfo | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/gdb/NEWS b/gdb/NEWS index 2a384ba..e079766 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -5684,3 +5684,8 @@ Host is the machine where GDB will run; targ is the machine where the program that you are debugging will run. * GDB now supports access to Intel(R) MPX registers on GNU/Linux. + + * Support for Intel(R) AVX-512 registers on GNU/Linux. + +Support displaying and modifying Intel(R) AVX-512 registers $zmm0 - $zmm31 and +$k0 - $k7 on GNU/Linux. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index de5ac63..14383c5 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -39041,6 +39041,40 @@ Memory Protection Extension (MPX). It should describe the following registers: The @samp{org.gnu.gdb.i386.linux} feature is optional. It should describe a single register, @samp{orig_eax}. +The @samp{org.gnu.gdb.i386.avx512} feature is optional and requires the +@samp{org.gnu.gdb.i386.avx} feature. It should +describe additional @sc{xmm} registers: + +@itemize @minus +@item +@samp{xmm16h} through @samp{xmm31h}, only valid for amd64. +@end itemize + +It should describe the upper 128 bits of additional @sc{ymm} registers: + +@itemize @minus +@item +@samp{ymm16h} through @samp{ymm31h}, only valid for amd64. +@end itemize + +It should +describe the upper 256 bits of @sc{zmm} registers: + +@itemize @minus +@item +@samp{zmm0h} through @samp{zmm7h} for i386. +@item +@samp{zmm0h} through @samp{zmm15h} for amd64. +@end itemize + +It should +describe the additional @sc{zmm} registers: + +@itemize @minus +@item +@samp{zmm16h} through @samp{zmm31h}, only valid for amd64. +@end itemize + @node MIPS Features @subsection @acronym{MIPS} Features @cindex target descriptions, @acronym{MIPS} features -- 1.8.4.2