From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7965 invoked by alias); 3 Dec 2013 12:37:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 7951 invoked by uid 89); 3 Dec 2013 12:37:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL,BAYES_50,RDNS_NONE,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mga03.intel.com Received: from Unknown (HELO mga03.intel.com) (143.182.124.21) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Dec 2013 12:36:44 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by azsmga101.ch.intel.com with ESMTP; 03 Dec 2013 04:36:22 -0800 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga001.fm.intel.com with ESMTP; 03 Dec 2013 04:36:21 -0800 Received: from ulvlx001.iul.intel.com (ulvlx001.iul.intel.com [172.28.207.17]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id rB3CaKQh028141; Tue, 3 Dec 2013 12:36:20 GMT Received: from ulvlx001.iul.intel.com (localhost [127.0.0.1]) by ulvlx001.iul.intel.com with ESMTP id rB3CaKBO014454; Tue, 3 Dec 2013 13:36:20 +0100 Received: (from wtedesch@localhost) by ulvlx001.iul.intel.com with œ id rB3CaJ2s014449; Tue, 3 Dec 2013 13:36:19 +0100 From: Walfred Tedeschi To: eliz@gnu.org Cc: gdb-patches@sourceware.org, Walfred Tedeschi Subject: [PATCH v3 1/1] Documentation for MPX. Date: Tue, 03 Dec 2013 12:37:00 -0000 Message-Id: <1386074172-14177-1-git-send-email-walfred.tedeschi@intel.com> X-IsSubscribed: yes X-SW-Source: 2013-12/txt/msg00082.txt.bz2 Eli, Thanks for your review! Phrase starting with: "Architecture registers BND0 through ..." now reads: "BND0 through ..." Thanks again and regards, -Fred 2013-12-03 Walfred Tedeschi * NEWS: Add section for Intel(R) Architecture Instructions Extesions mentioning MPX. doc/ * gdb.texinfo (i386 Features): Add MPX feature registers. (x86 Specific featuresx86 Architecture-specific Issues): Adds a subsubsection for MPX and describes the display of the boundary registers. --- gdb/NEWS | 2 ++ gdb/doc/gdb.texinfo | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/gdb/NEWS b/gdb/NEWS index 5110b27..dbc72a6 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -5563,3 +5563,5 @@ GDB now handles cross debugging. If you are remotely debugging between two different machines, type ``./configure host -target=targ''. Host is the machine where GDB will run; targ is the machine where the program that you are debugging will run. + + * GDB now supports access to Intel(R) MPX registers on GNU/Linux. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 004c376..ad496d0 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -21376,6 +21376,39 @@ be returned in a register. @kindex show struct-convention Show the current setting of the convention to return @code{struct}s from functions. + +@cindex Intel(R) Memory Protection Extensions (MPX). +@subsubsection Intel(R) @dfn{Memory Protection Extensions} (MPX). + +@item bnd0raw..bnd3raw and bnd0@dots{}bnd3 registers display. +Memory Protection Extension (MPX) adds the bound registers @samp{BND0} +@footnote{The register named with capital letters represent the architecture +registers.} through @samp{BND3}. Bound registers store a pair of 64-bit values +which are the lower bound and upper bound. Bounds are effective addresses or +memory locations. The upper bounds are architecturally represented in 1's +complement form. A bound having lower bound = 0, and upper bound = 0 +(1's complement of all bits set) will allow access to the entire address space. + +@samp{BND0} through @samp{BND3} are represented in @value{GDBN} as @samp{bnd0raw} +through @samp{bnd3raw}. Pseudo registers @samp{bnd0} through @samp{bnd3} +display the upper bound performing the complement of one operation on the +upper bound value, i.e.@ when upper bound in @samp{bnd0raw} is 0 in the +@value{GDBN} @samp{bnd0} it will be @code{0xfff@dots{}}. In this sense it +can also be noted that the upper bounds are inclusive. + +As an example, assume that the register BND0 holds bounds for a pointer having +access allowed for the range between 0x32 and 0x71. The values present on +bnd0raw and bnd registers are presented as follows: + +@smallexample + bnd0raw = @{0x32, 0xffffffff8e@} + bnd0 = @{lbound = 0x32, ubound = 0x71@} : size 64 +@end smallexample + +This way the raw value can be accessed via bnd0raw@dots{}bnd3raw. Any change +on bnd0@dots{}bnd3 or bnd0raw@dots{}bnd3raw is reflect on its counterpart. When the +bnd0@dots{}bnd3 registers are displayed via Python, the display includes the memory size, +in bits, accessible to the pointer. @end table @node Alpha @@ -43162,6 +43195,16 @@ describe the upper 128 bits of @sc{ymm} registers: @samp{ymm0h} through @samp{ymm15h} for amd64 @end itemize +The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R) +Memory Protection Extension (MPX). It should describe the following registers: + +@itemize @minus +@item +@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64. +@item +@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64. +@end itemize + The @samp{org.gnu.gdb.i386.linux} feature is optional. It should describe a single register, @samp{orig_eax}. -- 1.8.3.2