From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22540 invoked by alias); 21 Nov 2013 14:03:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 22501 invoked by uid 89); 21 Nov 2013 14:03:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.2 required=5.0 tests=BAYES_50,INVALID_MSGID,RDNS_NONE,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mga02.intel.com Received: from Unknown (HELO mga02.intel.com) (134.134.136.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 21 Nov 2013 14:03:46 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 21 Nov 2013 06:03:11 -0800 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga001.jf.intel.com with ESMTP; 21 Nov 2013 06:03:10 -0800 Received: from ulvlx001.iul.intel.com (ulvlx001.iul.intel.com [172.28.207.17]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id rALE39ir027666; Thu, 21 Nov 2013 14:03:09 GMT Received: from ulvlx001.iul.intel.com (localhost [127.0.0.1]) by ulvlx001.iul.intel.com with ESMTP id rALE39uP005640; Thu, 21 Nov 2013 15:03:09 +0100 Received: (from wtedesch@localhost) by ulvlx001.iul.intel.com with œ id rALE38FE005636; Thu, 21 Nov 2013 15:03:08 +0100 From: y@ecsmtp.iul.intel.com To: palves@redhat.com, eliz@gnu.org Cc: gdb-patches@sourceware.org, Walfred Tedeschi Subject: [PATCH 1/1] Documentation for MPX. Date: Thu, 21 Nov 2013 14:04:00 -0000 Message-Id: <1385042577-5600-1-git-send-email-y> In-Reply-To: References: X-SW-Source: 2013-11/txt/msg00628.txt.bz2 From: Walfred Tedeschi Hello Eli and Pedro, This should complement the MPX registers check-in in terms of documentation. Here I have tried to incorporate feedback from you both. Thanks a lot for your review on the former patch series. Best regards, -Fred 2013-1X-XX Walfred Tedeschi * NEWS: Add section for Intel(R) Architecture Instructions Extesions mentioning MPX. doc/ * gdb.texinfo (i386 Features): Add MPX feature registers. (x86 Specific featuresx86 Architecture-specific Issues): Adds a subsubsection for MPX and describes the display of the boundary registers. --- gdb/NEWS | 2 ++ gdb/doc/gdb.texinfo | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 0 deletions(-) diff --git a/gdb/NEWS b/gdb/NEWS index 9fc3638..fdb33d4 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -5558,3 +5558,5 @@ GDB now handles cross debugging. If you are remotely debugging between two different machines, type ``./configure host -target=targ''. Host is the machine where GDB will run; targ is the machine where the program that you are debugging will run. + + * GDB now supports access to Intel(R) MPX registers on GNU/Linux. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index d854f46..6041b4a 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -21363,6 +21363,42 @@ be returned in a register. @kindex show struct-convention Show the current setting of the convention to return @code{struct}s from functions. + +@subsubsection Intel(R) Memory Protection Extensions (MPX). + +@item bnd0raw..bnd3raw and bnd0...bnd3 registers display. +Memory Protection Extension (MPX) adds the bound registers @samp{BND0} +@footnote{Capital letters are used to distinguish between architecture +registers and pseudo registers. A set of pseudo registers for the bound +registers is created to simplify the display.} through @samp{BND3}. Bound +registers store a pair of 64-bit values which are the lower bound and upper +bound. Bounds are effective addresses or memory locations. The upper bounds +are architecturally represented in 1's complement form. A bound having lower +bound = 0, and upper bound = 0 (1's complement of all bits set) will allow +access to the entire address space. + +Architectuere registers @samp{BND0} through @samp{BND3} are +represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}. +Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound +performing the complement of one operation on the upper bound value, i.e.@ +when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will +be @code{0xfff...}. In this sense it can also be noted that the upper bounds are +inclusive. + +As an example, assume that the register BND0 holds bounds for a pointer having +access allowed for the range between 0x32 and 0x71. The values present on +bnd0raw and bnd registers are presented as follows: + +@smallexample + bnd0raw = {0x32, 0xffffffff8e} + bnd0 = {lbound = 0x32, ubound = 0x71} : size 64 +@end smallexample + +This way the architecture value can be accessed via bnd0raw...bnd3raw. Any change +on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart. When displaying +bnd0..bnd3 register with Python support also the size of the bounds is displayed. + + @end table @node Alpha @@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers: @samp{ymm0h} through @samp{ymm15h} for amd64 @end itemize +The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R) +Memory Protection Extension (MPX). It should describe the following registers: + +@itemize @minus +@item +@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64. +@item +@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64. +@end itemize + The @samp{org.gnu.gdb.i386.linux} feature is optional. It should describe a single register, @samp{orig_eax}. -- 1.7.6.5