From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23757 invoked by alias); 5 Sep 2013 09:26:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 23716 invoked by uid 89); 5 Sep 2013 09:26:47 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Sep 2013 09:26:47 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RDNS_NONE autolearn=no version=3.3.2 X-HELO: mga09.intel.com Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 05 Sep 2013 02:23:46 -0700 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga002.jf.intel.com with ESMTP; 05 Sep 2013 02:26:41 -0700 Received: from ulslx001.iul.intel.com (ulslx001.iul.intel.com [172.28.207.63]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id r859QeKr001766; Thu, 5 Sep 2013 10:26:40 +0100 Received: from ulslx001.iul.intel.com (localhost [127.0.0.1]) by ulslx001.iul.intel.com with ESMTP id r859QeSj031249; Thu, 5 Sep 2013 11:26:40 +0200 Received: (from wtedesch@localhost) by ulslx001.iul.intel.com with id r859Qe7n031245; Thu, 5 Sep 2013 11:26:40 +0200 From: Walfred Tedeschi To: tromey@redhat.com, gdb-patches@sourceware.org, mark.kettenis@xs4all.nl Cc: Walfred Tedeschi Subject: [PATCH V4 8/8] Add MPX feature description to GDB manual. Date: Thu, 05 Sep 2013 09:26:00 -0000 Message-Id: <1378373188-31144-9-git-send-email-walfred.tedeschi@intel.com> In-Reply-To: <1378373188-31144-1-git-send-email-walfred.tedeschi@intel.com> References: <1378373188-31144-1-git-send-email-walfred.tedeschi@intel.com> X-IsSubscribed: yes X-SW-Source: 2013-09/txt/msg00153.txt.bz2 Describes MPX feature registers including bnd0raw ... bnd3raw, bnd0 ... bnd3 bndstatus and bndcfgu. News adds the section for Intel(R) Architecture Instructions Extensions and mention the MPX support. 2013-08-30 Walfred Tedeschi * NEWS: Add section for Intel(R) Architecture Instructions Extesions mentioning MPX. doc/ * gdb.texinfo (i386 Features): Add MPX feature. --- gdb/NEWS | 2 ++ gdb/doc/gdb.texinfo | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/gdb/NEWS b/gdb/NEWS index ca8baea..fc58cc4 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -5464,3 +5464,5 @@ GDB now handles cross debugging. If you are remotely debugging between two different machines, type ``./configure host -target=targ''. Host is the machine where GDB will run; targ is the machine where the program that you are debugging will run. + + * GDB now supports access to Intel(R) MPX registers on GNU/Linux. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 21250fe..9f66992 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -42563,6 +42563,28 @@ describe the upper 128 bits of @sc{ymm} registers: The @samp{org.gnu.gdb.i386.linux} feature is optional. It should describe a single register, @samp{orig_eax}. +The @samp{org.gnu.gdb.i386.mpx} feature is optional. It should +describe the following registers: + +@itemize @minus +@item +@samp{bnd0raw} through @samp{bnd3raw} for i386, amd64 and x32. Hardware +representation of the bound registers effectively @samp{bnd0} through +@samp{bnd3}. The bounds are unsigned effective addresses, and are +inclusive. The upper bounds are architecturally represented in 1's +complement form. Lower bound = 0, and upper bound = 0 +(1's complement of all 1s) will allow access to the entire address +space. +@item +@samp{bnd0} through @samp{bnd3} for i386, amd64 and x32. +User representation of the bound registers. Upper bound value stores +the effective address of the bound, i.e. the one's complement of the +value stored on the upper bound of @samp{bndraw} registers. +@item +@samp{bndcfgu} and @samp{bndstatus} for i386, amd64 and x32. +@end itemize + + @node MIPS Features @subsection @acronym{MIPS} Features @cindex target descriptions, @acronym{MIPS} features -- 1.7.10.4