From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 836 invoked by alias); 14 Dec 2012 15:03:11 -0000 Received: (qmail 706 invoked by uid 22791); 14 Dec 2012 15:03:10 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RCVD_IN_HOSTKARMA_NO,RP_MATCHES_RCVD,TW_CN,TW_EG,TW_YM X-Spam-Check-By: sourceware.org Received: from rock.gnat.com (HELO rock.gnat.com) (205.232.38.15) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 14 Dec 2012 15:02:57 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id E8B151C706B; Fri, 14 Dec 2012 10:02:56 -0500 (EST) Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id kr3vQKJEt+cz; Fri, 14 Dec 2012 10:02:56 -0500 (EST) Received: from joel.gnat.com (localhost.localdomain [127.0.0.1]) by rock.gnat.com (Postfix) with ESMTP id 286271C69B3; Fri, 14 Dec 2012 10:02:56 -0500 (EST) Received: by joel.gnat.com (Postfix, from userid 1000) id 0297EC14D6; Fri, 14 Dec 2012 19:02:46 +0400 (RET) From: Joel Brobecker To: gdb-patches@sourceware.org Cc: Joel Brobecker Subject: [RFA 3/3] Add ravenscar-thread support for powerpc. Date: Fri, 14 Dec 2012 15:03:00 -0000 Message-Id: <1355497356-13922-3-git-send-email-brobecker@adacore.com> In-Reply-To: <1355497356-13922-1-git-send-email-brobecker@adacore.com> References: <1355497356-13922-1-git-send-email-brobecker@adacore.com> Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-12/txt/msg00502.txt.bz2 This patch adds ravenscar-thread support for PowerPC. There are two variants, which differ only by the list and location of their registers. gdb/ChangeLog: * ravenscar-ppc-thread.h, ravenscar-ppc-thread.c: New files. * Makefile.in (ALL_TARGET_OBS): Add ravenscar-ppc-thread.o. (HFILES_NO_SRCDIR): Add ravenscar-ppc-thread.h. (ALLDEPFILES): Add ravenscar-ppc-thread.c. * configure.tgt: Add ravenscar-ppc-thread.o to gdb_target_obs for every target that uses rs6000-tdep.o. * rs6000-tdep.c: #include "ravenscar-ppc-thread.h". (rs6000_gdbarch_init): Call register_e500_ravenscar_ops or register_ppc_ravenscar_ops. Tested on x86_64-linux. Also tested on powerpc-elf with AdaCore's testsuite. --- gdb/Makefile.in | 6 +- gdb/configure.tgt | 12 +- gdb/ravenscar-ppc-thread.c | 291 ++++++++++++++++++++++++++++++++++++++++++++ gdb/ravenscar-ppc-thread.h | 29 +++++ gdb/rs6000-tdep.c | 7 ++ 5 files changed, 337 insertions(+), 8 deletions(-) create mode 100644 gdb/ravenscar-ppc-thread.c create mode 100644 gdb/ravenscar-ppc-thread.h diff --git a/gdb/Makefile.in b/gdb/Makefile.in index 03f9693..b92f99a 100644 --- a/gdb/Makefile.in +++ b/gdb/Makefile.in @@ -563,7 +563,7 @@ ALL_TARGET_OBS = \ nto-tdep.o \ ppc-linux-tdep.o ppcnbsd-tdep.o ppcobsd-tdep.o ppc-sysv-tdep.o \ rl78-tdep.o \ - rs6000-aix-tdep.o rs6000-tdep.o \ + rs6000-aix-tdep.o rs6000-tdep.o ravenscar-ppc-thread.o \ rx-tdep.o \ s390-tdep.o \ score-tdep.o \ @@ -829,7 +829,7 @@ gnulib/import/stddef.in.h gnulib/import/inttypes.in.h inline-frame.h skip.h \ common/common-utils.h common/xml-utils.h common/buffer.h common/ptid.h \ common/format.h common/host-defs.h utils.h \ common/linux-osdata.h gdb-dlfcn.h auto-load.h probe.h stap-probe.h \ -gdb_bfd.h ravenscar-sparc-thread.h +gdb_bfd.h ravenscar-sparc-thread.h ravenscar-ppc-thread.h # Header files that already have srcdir in them, or which are in objdir. @@ -1485,7 +1485,7 @@ ALLDEPFILES = \ remote-sim.c \ dcache.c \ rl78-tdep.c \ - rs6000-nat.c rs6000-tdep.c \ + rs6000-nat.c rs6000-tdep.c ravenscar-ppc-thread.c \ rx-tdep.c \ s390-tdep.c s390-nat.c \ score-tdep.c \ diff --git a/gdb/configure.tgt b/gdb/configure.tgt index 8c442a7..f7218bd 100644 --- a/gdb/configure.tgt +++ b/gdb/configure.tgt @@ -386,31 +386,33 @@ mt-*-*) powerpc-*-netbsd* | powerpc-*-knetbsd*-gnu) # Target: NetBSD/powerpc gdb_target_obs="rs6000-tdep.o ppc-sysv-tdep.o ppcnbsd-tdep.o \ - solib-svr4.o" + solib-svr4.o ravenscar-ppc-thread.o" gdb_sim=../sim/ppc/libsim.a ;; powerpc-*-openbsd*) # Target: OpenBSD/powerpc gdb_target_obs="rs6000-tdep.o ppc-sysv-tdep.o ppcobsd-tdep.o \ - solib-svr4.o" + solib-svr4.o ravenscar-ppc-thread.o" ;; powerpc-*-aix* | rs6000-*-*) # Target: PowerPC running AIX gdb_target_obs="rs6000-tdep.o rs6000-aix-tdep.o xcoffread.o \ - ppc-sysv-tdep.o solib-svr4.o" + ppc-sysv-tdep.o solib-svr4.o ravenscar-ppc-thread.o" ;; powerpc-*-linux* | powerpc64-*-linux*) # Target: PowerPC running Linux gdb_target_obs="rs6000-tdep.o ppc-linux-tdep.o ppc-sysv-tdep.o \ solib-svr4.o solib-spu.o spu-multiarch.o \ - glibc-tdep.o symfile-mem.o linux-tdep.o" + glibc-tdep.o symfile-mem.o linux-tdep.o \ + ravenscar-ppc-thread.o" gdb_sim=../sim/ppc/libsim.a build_gdbserver=yes ;; powerpc*-*-*) # Target: PowerPC running eabi gdb_target_obs="rs6000-tdep.o monitor.o dsrec.o ppcbug-rom.o \ - dink32-rom.o ppc-sysv-tdep.o solib-svr4.o" + dink32-rom.o ppc-sysv-tdep.o solib-svr4.o \ + ravenscar-ppc-thread.o" if test -f ../sim/ppc/Makefile; then gdb_sim=../sim/ppc/libsim.a fi diff --git a/gdb/ravenscar-ppc-thread.c b/gdb/ravenscar-ppc-thread.c new file mode 100644 index 0000000..adc5c62 --- /dev/null +++ b/gdb/ravenscar-ppc-thread.c @@ -0,0 +1,291 @@ +/* Ravenscar PowerPC target support. + + Copyright 2011-2012 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "defs.h" +#include "gdbcore.h" +#include "regcache.h" +#include "ppc-tdep.h" +#include "inferior.h" +#include "ravenscar-thread.h" +#include "ravenscar-ppc-thread.h" + +#define NO_OFFSET -1 + +/* See ppc-tdep.h for register numbers. */ + +static const int powerpc_context_offsets[] = +{ + /* R0 - R32 */ + NO_OFFSET, 0, 4, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, 8, 12, 16, + 20, 24, 28, 32, + 36, 40, 44, 48, + 52, 56, 60, 64, + 68, 72, 76, 80, + + /* F0 - F31 */ + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, 96, 104, + 112, 120, 128, 136, + 144, 152, 160, 168, + 176, 184, 192, 200, + 208, 216, 224, 232, + + /* PC, MSR, CR, LR */ + 88, NO_OFFSET, 84, NO_OFFSET, + + /* CTR, XER, FPSCR */ + NO_OFFSET, NO_OFFSET, 240 +}; + +static const int e500_context_offsets[] = +{ + /* R0 - R32 */ + NO_OFFSET, 4, 12, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, 20, 28, 36, + 44, 52, 60, 68, + 76, 84, 92, 100, + 108, 116, 124, 132, + 140, 148, 156, 164, + + /* F0 - F31 */ + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + + /* PC, MSR, CR, LR */ + 172, NO_OFFSET, 168, NO_OFFSET, + + /* CTR, XER, FPSCR, MQ */ + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + + /* Upper R0-R32. */ + NO_OFFSET, 0, 8, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, + NO_OFFSET, 16, 24, 32, + 40, 48, 56, 64, + 72, 80, 88, 96, + 104, 112, 120, 128, + 136, 144, 152, 160, + + /* ACC, FSCR */ + NO_OFFSET, 176 +}; + +/* The register layout info. */ + +struct ravenscar_reg_info +{ + /* A table providing the offset relative to the context structure + where each register is saved. */ + const int *context_offsets; + + /* The number of elements in the context_offsets table above. */ + int context_offsets_size; +}; + +/* supply register REGNUM, which has been saved on REGISTER_ADDR, to the + regcache. */ + +static void +supply_register_at_address (struct regcache *regcache, int regnum, + CORE_ADDR register_addr) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + int buf_size = register_size (gdbarch, regnum); + char *buf; + + buf = (char *) alloca (buf_size); + read_memory (register_addr, buf, buf_size); + regcache_raw_supply (regcache, regnum, buf); +} + +/* Return true if, for a non-running thread, REGNUM has been saved on the + Thread_Descriptor. */ + +static int +register_in_thread_descriptor_p (const struct ravenscar_reg_info *reg_info, + int regnum) +{ + return (regnum < reg_info->context_offsets_size + && reg_info->context_offsets[regnum] != NO_OFFSET); +} + +/* to_fetch_registers when inferior_ptid is different from the running + thread. */ + +static void +ravenscar_generic_ppc_fetch_registers + (const struct ravenscar_reg_info *reg_info, + struct regcache *regcache, int regnum) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + const int sp_regnum = gdbarch_sp_regnum (gdbarch); + const int num_regs = gdbarch_num_regs (gdbarch); + int current_regnum; + CORE_ADDR current_address; + CORE_ADDR thread_descriptor_address; + + /* The tid is the thread_id field, which is a pointer to the thread. */ + thread_descriptor_address = (CORE_ADDR) ptid_get_tid (inferior_ptid); + + /* Read registers. */ + for (current_regnum = 0; current_regnum < num_regs; current_regnum++) + { + if (register_in_thread_descriptor_p (reg_info, current_regnum)) + { + current_address = thread_descriptor_address + + reg_info->context_offsets[current_regnum]; + supply_register_at_address (regcache, current_regnum, + current_address); + } + } +} + +/* to_prepare_to_store when inferior_ptid is different from the running + thread. */ + +static void +ravenscar_generic_ppc_prepare_to_store (struct regcache *regcache) +{ + /* Nothing to do. */ +} + +/* to_store_registers when inferior_ptid is different from the running + thread. */ + +static void +ravenscar_generic_ppc_store_registers + (const struct ravenscar_reg_info *reg_info, + struct regcache *regcache, int regnum) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + int buf_size = register_size (gdbarch, regnum); + char buf [buf_size]; + ULONGEST register_address; + + if (register_in_thread_descriptor_p (reg_info, regnum)) + register_address + = ptid_get_tid (inferior_ptid) + reg_info->context_offsets [regnum]; + else + return; + + regcache_raw_collect (regcache, regnum, buf); + write_memory (register_address, + buf, + buf_size); +} + +/* The ravenscar_reg_info for most PowerPC targets. */ + +static const struct ravenscar_reg_info ppc_reg_info = +{ + powerpc_context_offsets, + ARRAY_SIZE (powerpc_context_offsets), +}; + +/* Implement the to_fetch_registers ravenscar_arch_ops method + for most PowerPC targets. */ + +static void +ravenscar_powerpc_fetch_registers (struct regcache *regcache, int regnum) +{ + ravenscar_generic_ppc_fetch_registers (&ppc_reg_info, regcache, regnum); +} + +/* Implement the to_store_registers ravenscar_arch_ops method + for most PowerPC targets. */ + +static void +ravenscar_powerpc_store_registers (struct regcache *regcache, int regnum) +{ + ravenscar_generic_ppc_store_registers (&ppc_reg_info, regcache, regnum); +} + +/* The ravenscar_arch_ops vector for most PowerPC targets. */ + +static struct ravenscar_arch_ops ravenscar_powerpc_ops = +{ + ravenscar_powerpc_fetch_registers, + ravenscar_powerpc_store_registers, + ravenscar_generic_ppc_prepare_to_store +}; + +/* Register ravenscar_powerpc_ops in GDBARCH. */ + +void +register_ppc_ravenscar_ops (struct gdbarch *gdbarch) +{ + set_gdbarch_ravenscar_ops (gdbarch, &ravenscar_powerpc_ops); +} + +/* The ravenscar_reg_info for E500 targets. */ + +static const struct ravenscar_reg_info e500_reg_info = +{ + e500_context_offsets, + ARRAY_SIZE (e500_context_offsets), +}; + +/* Implement the to_fetch_registers ravenscar_arch_ops method + for E500 targets. */ + +static void +ravenscar_e500_fetch_registers (struct regcache *regcache, int regnum) +{ + ravenscar_generic_ppc_fetch_registers (&e500_reg_info, regcache, regnum); +} + +/* Implement the to_store_registers ravenscar_arch_ops method + for E500 targets. */ + +static void +ravenscar_e500_store_registers (struct regcache *regcache, int regnum) +{ + ravenscar_generic_ppc_store_registers (&e500_reg_info, regcache, regnum); +} + +/* The ravenscar_arch_ops vector for E500 targets. */ + +static struct ravenscar_arch_ops ravenscar_e500_ops = +{ + ravenscar_e500_fetch_registers, + ravenscar_e500_store_registers, + ravenscar_generic_ppc_prepare_to_store +}; + +/* Register ravenscar_e500_ops in GDBARCH. */ + +void +register_e500_ravenscar_ops (struct gdbarch *gdbarch) +{ + set_gdbarch_ravenscar_ops (gdbarch, &ravenscar_e500_ops); +} diff --git a/gdb/ravenscar-ppc-thread.h b/gdb/ravenscar-ppc-thread.h new file mode 100644 index 0000000..334153b --- /dev/null +++ b/gdb/ravenscar-ppc-thread.h @@ -0,0 +1,29 @@ +/* Ravenscar PowerPC target support. + + Copyright 2012 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef RAVENSCAR_PPC_THREAD_H +#define RAVENSCAR_PPC_THREAD_H + +struct gdbarch; + +extern void register_ppc_ravenscar_ops (struct gdbarch *gdbarch); + +extern void register_e500_ravenscar_ops (struct gdbarch *gdbarch); + +#endif diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 07b81bc..95b5e1b 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -52,6 +52,7 @@ #include "solib-svr4.h" #include "ppc-tdep.h" +#include "ravenscar-ppc-thread.h" #include "gdb_assert.h" #include "dis-asm.h" @@ -4153,6 +4154,12 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) gdb_assert (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); + /* Register the ravenscar_arch_ops. */ + if (mach == bfd_mach_ppc_e500) + register_e500_ravenscar_ops (gdbarch); + else + register_ppc_ravenscar_ops (gdbarch); + return gdbarch; } -- 1.7.10.4