From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23813 invoked by alias); 7 Dec 2012 10:35:58 -0000 Received: (qmail 23791 invoked by uid 22791); 7 Dec 2012 10:35:57 -0000 X-SWARE-Spam-Status: No, hits=-7.2 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_DNSWL_HI,RCVD_IN_HOSTKARMA_W,RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 07 Dec 2012 10:35:52 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 07 Dec 2012 02:35:52 -0800 X-ExtLoop1: 1 Received: from swsutil001.isw.intel.com ([10.237.237.11]) by fmsmga002.fm.intel.com with ESMTP; 07 Dec 2012 02:35:50 -0800 Received: from ulslx001.iul.intel.com (ulslx001.iul.intel.com [172.28.207.63]) by swsutil001.isw.intel.com (8.13.6/8.13.6/MailSET/Hub) with ESMTP id qB7AZneA031616; Fri, 7 Dec 2012 10:35:49 GMT Received: from ulslx001.iul.intel.com (localhost [127.0.0.1]) by ulslx001.iul.intel.com with ESMTP id qB7AZmVM025640; Fri, 7 Dec 2012 11:35:48 +0100 Received: (from mmetzger@localhost) by ulslx001.iul.intel.com with id qB7AZemB025636; Fri, 7 Dec 2012 11:35:40 +0100 From: markus.t.metzger@intel.com To: mingo@redhat.com, mingo@elte.hu Cc: markus.t.metzger@intel.com, linux-kernel@vger.kernel.org, Mark Kettenis , Pedro Alves , Jan Kratochvil , gdb-patches@sourceware.org Subject: [PATCH] x86, perf, bts: disable BTS from Nehalem to Ivy Bridge Date: Fri, 07 Dec 2012 10:35:00 -0000 Message-Id: <1354876511-25294-1-git-send-email-markus.t.metzger@intel.com> X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-12/txt/msg00145.txt.bz2 From: Markus Metzger Starting with Nehalem, the BTS "from" information may in some cases be incorrect (AAJ122). This has been detected while adding branch tracing support to gdb, where it results in sporadic test fails. Disable BTS support on Nehalem, Westmere, Sandy Bridge, and Ivy Bridge. CC: Mark Kettenis CC: Pedro Alves CC: Jan Kratochvil CC: gdb-patches@sourceware.org Signed-off-by: Markus Metzger --- arch/x86/kernel/cpu/perf_event_intel.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 6bca492..e72aac9 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1893,6 +1893,16 @@ static __init void intel_nehalem_quirk(void) } } +static __init void intel_disable_bts(void) +{ + /* + * Erratum AAJ122: LBR, BTM, or BTS records may have incorrect branch + * "from" information afer an EIST transition, T-states, C1E, or + * Adaptive Thermal Throttling. + */ + x86_pmu.bts = 0; +} + __init int intel_pmu_init(void) { union cpuid10_edx edx; @@ -2003,6 +2013,7 @@ __init int intel_pmu_init(void) X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); x86_add_quirk(intel_nehalem_quirk); + intel_disable_bts(); pr_cont("Nehalem events, "); break; @@ -2042,6 +2053,7 @@ __init int intel_pmu_init(void) intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); + intel_disable_bts(); pr_cont("Westmere events, "); break; @@ -2070,6 +2082,7 @@ __init int intel_pmu_init(void) intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); + intel_disable_bts(); pr_cont("SandyBridge events, "); break; case 58: /* IvyBridge */ @@ -2092,6 +2105,7 @@ __init int intel_pmu_init(void) intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); + intel_disable_bts(); pr_cont("IvyBridge events, "); break; -- 1.7.1