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Fri, 17 Jul 2026 16:27:01 +0000 Date: Fri, 17 Jul 2026 16:26:56 +0000 (UTC) From: Hannes Domani To: "gdb-patches@sourceware.org" , "Schimpe, Christina" Message-ID: <1319283533.3531812.1784305616658@mail.yahoo.com> In-Reply-To: References: <20260712113229.3695246-1-ssbssa@yahoo.de> <20260712113229.3695246-7-ssbssa@yahoo.de> <1783589955.3451825.1784296008828@mail.yahoo.com> <1971012298.3491204.1784299790735@mail.yahoo.com> Subject: Re: [PATCH 7/8] Windows gdb: Implement XState (Intel AVX) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Mailer: WebService/1.1.26136 YMailNorrin X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Am Freitag, 17. Juli 2026 um 17:26:14 MESZ hat Schimpe, Christina Folgendes geschrieben: > > -----Original Message----- > > From: Hannes Domani > > Sent: Freitag, 17. Juli 2026 16:50 > > To: gdb-patches@sourceware.org; Schimpe, Christina > > > > Subject: Re: [PATCH 7/8] Windows gdb: Implement XState (Intel AVX) supp= ort > > > >=C2=A0 Am Freitag, 17. Juli 2026 um 16:16:31 MESZ hat Schimpe, Christina > > Folgendes geschrieben: > > > > > > -----Original Message----- > > > > From: Hannes Domani > > > > Sent: Freitag, 17. Juli 2026 15:47 > > > > To: gdb-patches@sourceware.org; Schimpe, Christina > > > > > > > > Subject: Re: [PATCH 7/8] Windows gdb: Implement XState (Intel AVX) > > > > support > > > > > > > >=C2=A0 Am Freitag, 17. Juli 2026 um 14:54:59 MESZ hat Schimpe, Chris= tina > > > > Folgendes geschrieben: > > > > > > > > > Hi Hannes, > > > > > > > > > > Thank you for working on this. > > > > > It appears that this patch uses the same commit message header as > > > > > patch #8. Is it intentional that these are separate commits? > > > > > > > > This one is the gdb part, and #8 is the gdbserver part, that is > > > > stated in the title. > > > > > > Oups, I wonder how I came to that conclusion.=C2=A0 Sorry for that. > > > > > > > > > > > > In any case, IMO, commit messages should not have identical heade= rs. > > > > > Also, this patch seems big enough for a commit message which is > > > > > not header only. :) > > > > > > This part still stands for the commit message. Since it's not only av= x > > > registers, I believe it makes sense to share more details here. > > > > Yes, I will do that. > > > > > > > > > Do any AVX-* specific tests pass on Windows now? If so, it would > > > > > be helpful to mention that in the commit message as well. > > > > > > > > I actually planned to add that info, but forgot. > > > > > > > > These tests then pass on Windows: > > > > gdb.arch/i386-avx.exp > > > > gdb.arch/i386-avx512.exp > > > > > > What's the state for SSE=C2=A0 (gdb.arch/i386-sse.exp) ? > > > > i386-sse.exp works since patch #1, it was only a compile issue of the t= est > > itself. > > I will mention this in the patch as well. >=C2=A0 > Thanks. >=C2=A0 > > > > > I also saw you introduced some code for PKRU and the shadow stack > > pointer. > > > We have GDB tests for those registers, too: > > > - gdb.arch/i386-pkru.exp > > > - gdb.arch/amd64-shadow-stack*.exp > > > > For these I just added the equivalent code as is done on Linux, without= really > > knowing what they are for. > > > > i386-pkru.exp tells me: > > > > (gdb) print have_pkru() > > $1 =3D 0 > > (gdb) PASS: gdb.arch/i386-pkru.exp: probe PKRU support > > UNSUPPORTED: gdb.arch/i386-pkru.exp: processor does not support > > protection key feature. > > > > Do only certain CPU's have this register? >=C2=A0 > Most recent CPUs should have it. To be sure you can check if the correspo= nding bit > is configured in xcr0. I thought that's what have_pkru() does, but I might be wrong about that. > I believe for windows this should be the mask returned by get_xstate_feat= ures_mask. You probably mean GetEnabledXStateFeatures, but yes, it also tells me my CP= U doesn't support this. > If your cpu does have it, I think you must look at the test in more detai= l to find out why it's > unsupported. It might need some adaptions for windows. Google tells me only not all recent CPUs have this, is mine one of them?: 11th Gen Intel(R) Core(TM) i7-11850H > > And amd64-shadow-stack.exp: > > > > (gdb) print $pl3_ssp > > $1 =3D (void *) 0x0 > > (gdb) FAIL: gdb.arch/amd64-shadow-stack.exp: test shadow stack support > > > > No idea if that should work, since Windows is supplying data for the $p= l3_ssp > > register. > > > > > > Hannes >=C2=A0 > Without knowing any of the details in windows I believe adding full suppo= rt for CET shadow > stack might need some more changes. At least for linux, this was the case= : > https://inbox.sourceware.org/gdb-patches/20250821171029.1555603-1-christi= na.schimpe@intel.com/ >=C2=A0 > I believe it would be better to handle this in a separate patch-(series). > This also applies for any other register that you add and whose dedicated= test does not pass. >=C2=A0 > Does that make sense to you? I was wondering if it isn't the compiler or linker on windows (or maybe win= dows itself?) that doesn't support this -fcf-protection=3Dreturn stuff. Hannes