Re: [RFA] Fix Power7 extended floating point pseudo-registers

Thiago Jung Bauermann
2011-02-15T02:03:36Z

Hi Ulrich,

Thanks for the review.

On Mon, 2011-02-14 at 14:47 +0100, Ulrich Weigand wrote:
> Thiago Jung Bauermann wrote:
> > @@ -2720,10 +2720,12 @@ efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
> > {
> > struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
> > int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
> > + int vr_reg_nr = tdep->ppc_vr0_regnum + reg_index;
> > + gdb_byte vr_reg_buf[MAX_REGISTER_SIZE];
> >
> > - /* Read the portion that overlaps the VMX registers. */
> > - regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
> > - reg_index, buffer);
> > + /* Read the portion that overlaps the VMX register. */
> > + regcache_raw_read (regcache, vr_reg_nr, vr_reg_buf);
> > + memcpy (buffer, vr_reg_buf, register_size (gdbarch, reg_nr));
> > }
>
> This just re-implements regcache_raw_read_part, doesn't it? You should
> be just using that routine instead (and likewise for _write).

Indeed. I didn't know about regcache_raw_read_part. This version uses
that function (and the same for _write). Ok?
--
[]'s
Thiago Jung Bauermann
IBM Linux Technology Center

2011-02-15 Thiago Jung Bauermann <bauerman@br.ibm.com>

gdb/
* rs6000-tdep.c (IS_EFP_PSEUDOREG): Use correct constant for
the EFP register set size.
(efpr_pseudo_register_read): Use regcache_raw_read_part to read
data from the VMX register.
(efpr_pseudo_register_write): Use regcache_raw_write_part to read
and write data from/to the VMX register.

gdb/testsuite/
* gdb.arch/vsx-regs.exp: Add "vector_register1_vr" and
"vector_register2_vr" test strings. Test the extended floating
point registers (F32~F63).
* lib/gdb.exp (skip_vsx_tests): Update compile flags for the
IBM XL C compiler. Make the test program use a register provided
by the compiler for the lxvd2x instruction.

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 9832b5b..6ac3e8d 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -99,7 +99,7 @@
/* Determine if regnum is a POWER7 Extended FP register. */
#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_efpr0_regnum \
- && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
+ && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)

/* The list of available "set powerpc ..." and "show powerpc ..."
commands. */
@@ -2721,9 +2721,9 @@ efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int reg_index = reg_nr - tdep->ppc_efpr0_regnum;

- /* Read the portion that overlaps the VMX registers. */
- regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
- reg_index, buffer);
+ /* Read the portion that overlaps the VMX register. */
+ regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
+ register_size (gdbarch, reg_nr), buffer);
}

/* Write method for POWER7 Extended FP pseudo-registers. */
@@ -2734,9 +2734,9 @@ efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int reg_index = reg_nr - tdep->ppc_efpr0_regnum;

- /* Write the portion that overlaps the VMX registers. */
- regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
- reg_index, buffer);
+ /* Write the portion that overlaps the VMX register. */
+ regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
+ register_size (gdbarch, reg_nr), buffer);
}

static void
diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
index d42b7f3..959f90a 100644
--- a/gdb/testsuite/gdb.arch/vsx-regs.exp
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -66,8 +66,12 @@ if ![runto_main] then {

set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."

+set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+
set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."

+set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+
set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."

set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
@@ -123,6 +127,11 @@ for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
}

+# Create a core file. We create the core file before the F32~F63/VR0~VR31 test
+# below because then we'll have more interesting register values to verify
+# later when loading the core file (i.e., different register values for different
+# vector register banks).
+
set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]

set core_supported 0
@@ -142,6 +151,34 @@ gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
}
}

+# Now run the F32~F63/VR0~VR31 tests.
+
+# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
+for {set i 32} {$i < 64} {incr i 1} {
+ gdb_test_no_output "set \$f$i = 1\.3"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
+}
+
+# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
+for {set i 0} {$i < 32} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
+ }
+}
+
+for {set i 32} {$i < 64} {incr i 1} {
+ gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
+}
+
+# Test reading the core file.
+
if {!$core_supported} {
return -1
}
diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp
index 5a3f1fc..d523d8e 100644
--- a/gdb/testsuite/lib/gdb.exp
+++ b/gdb/testsuite/lib/gdb.exp
@@ -1686,7 +1686,7 @@ proc skip_vsx_tests {} {
if [test_compiler_info gcc*] {
set compile_flags "$compile_flags additional_flags=-mvsx"
} elseif [test_compiler_info xlc*] {
- set compile_flags "$compile_flags additional_flags=-qvsx"
+ set compile_flags "$compile_flags additional_flags=-qasm=gcc"
} else {
verbose "Could not compile with vsx support, returning 1" 2
return 1
@@ -1697,10 +1697,11 @@ proc skip_vsx_tests {} {

set f [open $src "w"]
puts $f "int main() {"
+ puts $f " double a\[2\] = { 1.0, 2.0 };"
puts $f "#ifdef __MACH__"
- puts $f " asm volatile (\"lxvd2x v0,v0,v0\");"
+ puts $f " asm volatile (\"lxvd2x v0,v0,%\[addr\]\" : : \[addr\] \"r\" (a));"
puts $f "#else"
- puts $f " asm volatile (\"lxvd2x 0,0,0\");"
+ puts $f " asm volatile (\"lxvd2x 0,0,%\[addr\]\" : : \[addr\] \"r\" (a));"
puts $f "#endif"
puts $f " return 0; }"
close $f