From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15675 invoked by alias); 18 Aug 2010 21:18:21 -0000 Received: (qmail 15321 invoked by uid 22791); 18 Aug 2010 21:18:18 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e24smtp01.br.ibm.com (HELO e24smtp01.br.ibm.com) (32.104.18.85) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 18 Aug 2010 21:17:08 +0000 Received: from d24relay01.br.ibm.com (d24relay01.br.ibm.com [9.8.31.16]) by e24smtp01.br.ibm.com (8.14.4/8.13.1) with ESMTP id o7ILNqCV004666 for ; Wed, 18 Aug 2010 18:23:52 -0300 Received: from d24av04.br.ibm.com (d24av04.br.ibm.com [9.8.31.97]) by d24relay01.br.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o7ILGj702486372 for ; Wed, 18 Aug 2010 18:16:45 -0300 Received: from d24av04.br.ibm.com (loopback [127.0.0.1]) by d24av04.br.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id o7ILH2YE004597 for ; Wed, 18 Aug 2010 18:17:02 -0300 Received: from [9.8.0.248] ([9.8.0.248]) by d24av04.br.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id o7ILH1uL003887; Wed, 18 Aug 2010 18:17:01 -0300 Subject: Re: [RFA] Fix setting of VSX registers From: Thiago Jung Bauermann To: Tom Tromey Cc: gdb-patches ml , Joel Brobecker In-Reply-To: References: <1279738729.11022.23.camel@hactar> Content-Type: text/plain; charset="UTF-8" Date: Wed, 18 Aug 2010 21:18:00 -0000 Message-ID: <1282166177.19094.10.camel@hactar> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-08/txt/msg00316.txt.bz2 Hi, [ Context: fix vsx-regs.exp testcase which was broken because of output changes in GDB. ] On Thu, 2010-07-22 at 10:05 -0600, Tom Tromey wrote: > >>>>> "Thiago" == Thiago Jung Bauermann writes: > Thiago> This patch fixes the typo, and also fixes the vsx-regs.exp testcase to > Thiago> use gdb_test instead of send_gdb (this also fixes some synchronization > Thiago> issues in the test), and updates the expect info reg output with the new > Thiago> v2_double member. > > I don't understand why the new gdb_test calls have an empty "message" > argument. > > Actually, this code in gdb_test itself looks somewhat bogus. > Aside from parsing arguments by hand (why??), it uses a different > default for the message than gdb_test_multiple. I don't understand when > this can ever be the right thing to do. > > For your patch I suggest just leaving off the 3rd argument. > > Also, when the second argument to gdb_test is the empty string ... I > suspect you actually want to use gdb_test_no_output. Decided to just give up the 3rd argument and make the set up commands count as tests too. Also changed to use gdb_test_no_output. Ok? Also, ok for the branch? -- []'s Thiago Jung Bauermann IBM Linux Technology Center 2010-08-18 Thiago Jung Bauermann * gdb.arch/vsx-regs.exp: Remove wrong comment about testing AltiVec registers. Update data sets with the new v2_double element in the VSX register union. Add vector_register3_vr data set for the AltiVec registers. Use gdb_test_no_output instead of send_gdb. Index: gdb.git/gdb/testsuite/gdb.arch/vsx-regs.exp =================================================================== --- gdb.git.orig/gdb/testsuite/gdb.arch/vsx-regs.exp 2010-07-29 16:49:32.000000000 -0300 +++ gdb.git/gdb/testsuite/gdb.arch/vsx-regs.exp 2010-08-18 16:11:13.000000000 -0300 @@ -14,8 +14,6 @@ # along with this program. If not, see . # -# Tests for Powerpc AltiVec register setting and fetching - if $tracelevel then { strace $tracelevel } @@ -66,11 +64,13 @@ if ![runto_main] then { # Data sets used throughout the test -set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." +set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." + +set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." -set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." +set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." -set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." +set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." set float_register ".raw 0xdeadbeefdeadbeef." @@ -78,7 +78,7 @@ set float_register ".raw 0xdeadbeefdeadb # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. for {set i 0} {$i < 32} {incr i 1} { - send_gdb "set \$f$i = 1\.3" + gdb_test_no_output "set \$f$i = 1\.3" } for {set i 0} {$i < 32} {incr i 1} { @@ -88,7 +88,7 @@ for {set i 0} {$i < 32} {incr i 1} { # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. for {set i 0} {$i < 32} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" + gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" } } @@ -105,7 +105,7 @@ for {set i 0} {$i < 32} {incr i 1} { # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. for {set i 0} {$i < 32} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vr$i.v4_int32\[$j\] = 1" + gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" } } @@ -115,12 +115,12 @@ for {set i 32} {$i < 64} {incr i 1} { # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. for {set i 32} {$i < 64} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vs$i.v4_int32\[$j\] = 1" + gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" } } for {set i 0} {$i < 32} {incr i 1} { - gdb_test "info reg vr$i" "vr$i.*$vector_register3" "info reg vr$i" + gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" } set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]