From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6921 invoked by alias); 3 Mar 2009 21:30:55 -0000 Received: (qmail 6912 invoked by uid 22791); 3 Mar 2009 21:30:54 -0000 X-SWARE-Spam-Status: No, hits=-1.3 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_21,SPF_SOFTFAIL X-Spam-Check-By: sourceware.org Received: from e9.ny.us.ibm.com (HELO e9.ny.us.ibm.com) (32.97.182.139) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 03 Mar 2009 21:30:48 +0000 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e9.ny.us.ibm.com (8.13.1/8.13.1) with ESMTP id n23LMW3u011431 for ; Tue, 3 Mar 2009 16:22:32 -0500 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay02.pok.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n23LUkqf193486 for ; Tue, 3 Mar 2009 16:30:46 -0500 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id n23LUklo012134 for ; Tue, 3 Mar 2009 16:30:46 -0500 Received: from [192.168.1.102] (vorma.rchland.ibm.com [9.10.86.174]) by d01av01.pok.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id n23LUixU012123; Tue, 3 Mar 2009 16:30:45 -0500 Subject: Re: [patch] Enable power7 disassembling From: Peter Bergner To: Jan Kratochvil Cc: gdb-patches@sourceware.org, Thiago Jung Bauermann , Alan Modra In-Reply-To: <20090302210404.GB23798@host0.dyn.jankratochvil.net> References: <20090302210404.GB23798@host0.dyn.jankratochvil.net> Content-Type: text/plain Date: Tue, 03 Mar 2009 21:30:00 -0000 Message-Id: <1236115864.6800.80.camel@otta> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2009-03/txt/msg00038.txt.bz2 On Mon, 2009-03-02 at 22:04 +0100, Jan Kratochvil wrote: > GDB has currently for PowerPC hardcoded disassembling `-Many' by the patch: > http://sourceware.org/ml/gdb-patches/2007-02/msg00000.html > http://sourceware.org/ml/gdb-cvs/2007-02/msg00061.html > > ./gas/as-new -mpower7 -o ./gas/testsuite/gas/ppc/power7.o ./gas/testsuite/gas/ppc/power7.s > objdump -d ./gas/testsuite/gas/ppc/power7.o > 20: f0 64 28 50 .long 0xf0642850 > objdump -Mpower7 -d ./gas/testsuite/gas/ppc/power7.o > 20: f0 64 28 50 xxmrghd vs3,vs4,vs5 > objdump -Many -d ./gas/testsuite/gas/ppc/power7.o > 20: f0 64 28 50 stfq f3,10320(r4) This is caused by primary opcode 60 being reused by POWER2 (which is actually not a Power ISA supported processor) and POWER7 (which is). The disassembler happily chooses the first matching instruction it comes across in the opcode table, which happens to be POWER2's stfq, so that's what we see. I think it might make sense to swap their order in the opcode table, so the processor more likely to be used is listed first. Alan, what do you think of the patch below? Heh, I'll note that stfq doesn't even disassemble with -Mpower2, since there is no code in ppc-dis.c that recognizes POWER2. Ditto for a lot of other processor names. > Therefore assuming there should be a new GDB option: > set powerpc disassembler-options power7 > which would still default to `any' as currently but one could override it. This still might be a good idea. I assume you could choose any valid ppc processor name accepted by the disassembler here? Eg, power4, power5, booke, etc. Peter opcodes/ * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that instructions from newer processors are listed before older ones. Index: opcodes/ppc-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/ppc-opc.c,v retrieving revision 1.117 diff -u -p -r1.117 ppc-opc.c --- opcodes/ppc-opc.c 26 Feb 2009 22:07:33 -0000 1.117 +++ opcodes/ppc-opc.c 3 Mar 2009 20:56:59 -0000 @@ -4560,8 +4560,8 @@ const struct powerpc_opcode powerpc_opco {"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, -{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}}, +{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, {"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, @@ -4638,8 +4638,8 @@ const struct powerpc_opcode powerpc_opco {"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, -{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, {"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}}, +{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, {"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -4801,12 +4801,12 @@ const struct powerpc_opcode powerpc_opco {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, +{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, + {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, -{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, - {"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, {"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, {"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, @@ -4921,10 +4921,6 @@ const struct powerpc_opcode powerpc_opco {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, -{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, - -{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, - {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, @@ -5067,12 +5063,16 @@ const struct powerpc_opcode powerpc_opco {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, +{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, -{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, +{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, {"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}}, +{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, + +{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, + {"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, {"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}},