From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13764 invoked by alias); 15 Aug 2008 15:29:34 -0000 Received: (qmail 13740 invoked by uid 22791); 15 Aug 2008 15:29:32 -0000 X-Spam-Check-By: sourceware.org Received: from igw2.br.ibm.com (HELO igw2.br.ibm.com) (32.104.18.25) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 15 Aug 2008 15:28:42 +0000 Received: from mailhub3.br.ibm.com (mailhub3 [9.18.232.110]) by igw2.br.ibm.com (Postfix) with ESMTP id D944217F7CF for ; Fri, 15 Aug 2008 12:14:31 -0300 (BRT) Received: from d24av01.br.ibm.com (d24av01.br.ibm.com [9.18.232.46]) by mailhub3.br.ibm.com (8.13.8/8.13.8/NCO v8.7) with ESMTP id m7FFSPjt3850492 for ; Fri, 15 Aug 2008 12:28:25 -0300 Received: from d24av01.br.ibm.com (loopback [127.0.0.1]) by d24av01.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m7FFSJfq000757 for ; Fri, 15 Aug 2008 12:28:19 -0300 Received: from [9.8.8.85] ([9.8.8.85]) by d24av01.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id m7FFSIm2000715 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 15 Aug 2008 12:28:18 -0300 Subject: Re: [PATCH-ppc 5/5] Add VSX doc bits From: Luis Machado Reply-To: luisgpm@linux.vnet.ibm.com To: gdb-patches@sourceware.org Cc: Eli Zaretskii In-Reply-To: <1217016956.29012.79.camel@gargoyle> References: <1217016956.29012.79.camel@gargoyle> Content-Type: text/plain Date: Fri, 15 Aug 2008 15:29:00 -0000 Message-Id: <1218814096.8946.39.camel@gargoyle> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-08/txt/msg00417.txt.bz2 Hi Eli, What do you think about the doc bits for this one? Regards, Luis On Fri, 2008-07-25 at 17:15 -0300, Luis Machado wrote: > Last, but not the least, this adds some documentation about the new > register set. It's not very descriptive, but as the patches may change a > bit, i'll leave this one to the end. It'll probably require a NEWS entry > as well. > > --- > 2008-07-25 Luis Machado > > * doc/gdb.texinfo: Updated documentation with new support info. > > Index: gdb/doc/gdb.texinfo > =================================================================== > --- gdb.orig/doc/gdb.texinfo 2008-07-23 09:28:06.000000000 -0700 > +++ gdb/doc/gdb.texinfo 2008-07-23 09:31:44.000000000 -0700 > @@ -16210,6 +16210,9 @@ > by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0}, > @code{f2} and @code{f3} for @code{$dl1} and so on. > > +For POWER7 processors, GDB provides a new set of pseudo-registers, the 64-bit > +wide Extended Floating Point Registers (@samp{f32} through @samp{f63}). > + > > @node Controlling GDB > @chapter Controlling @value{GDBN} > @@ -27406,6 +27409,13 @@ > contain registers @samp{vr0} through @samp{vr31}, @samp{vscr}, > and @samp{vrsave}. > > +The @samp{org.gnu.gdb.power.vsx} feature is optional. It should > +contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN} > +will combine these registers with the floating point registers > +(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0} > +through @samp{vr31}} to present the 128-bit wide registers @samp{vs0} > +through @samp{vs63}, the new set of vector registers for POWER7. > + > The @samp{org.gnu.gdb.power.spe} feature is optional. It should > contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and > @samp{spefscr}. SPE targets should provide 32-bit registers in > >