From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12767 invoked by alias); 26 Jul 2008 03:50:12 -0000 Received: (qmail 12757 invoked by uid 22791); 26 Jul 2008 03:50:11 -0000 X-Spam-Check-By: sourceware.org Received: from igw3.br.ibm.com (HELO igw3.br.ibm.com) (32.104.18.26) by sourceware.org (qpsmtpd/0.31) with ESMTP; Sat, 26 Jul 2008 03:49:43 +0000 Received: from mailhub1.br.ibm.com (unknown [9.18.232.109]) by igw3.br.ibm.com (Postfix) with ESMTP id 2E027390070 for ; Sat, 26 Jul 2008 00:31:02 -0300 (BRST) Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.18.232.47]) by mailhub1.br.ibm.com (8.13.8/8.13.8/NCO v9.0) with ESMTP id m6Q3nja12367566 for ; Sat, 26 Jul 2008 00:49:45 -0300 Received: from d24av02.br.ibm.com (loopback [127.0.0.1]) by d24av02.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m6Q3net0029946 for ; Sat, 26 Jul 2008 00:49:40 -0300 Received: from [9.18.203.75] ([9.18.203.75]) by d24av02.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id m6Q3nded029832 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 26 Jul 2008 00:49:39 -0300 Subject: Re: [PATCH-ppc 0/5] Add feature description for new VSX register set From: Luis Machado Reply-To: luisgpm@linux.vnet.ibm.com To: "Joseph S. Myers" Cc: Thiago Jung Bauermann , gdb-patches@sourceware.org In-Reply-To: References: <1217016935.29012.74.camel@gargoyle> <1217021353.5922.121.camel@localhost.localdomain> Content-Type: text/plain Date: Sat, 26 Jul 2008 03:50:00 -0000 Message-Id: <1217044165.29012.107.camel@gargoyle> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-07/txt/msg00470.txt.bz2 On Fri, 2008-07-25 at 21:45 +0000, Joseph S. Myers wrote: > On Fri, 25 Jul 2008, Thiago Jung Bauermann wrote: > > > On Fri, 2008-07-25 at 21:01 +0000, Joseph S. Myers wrote: > > > On Fri, 25 Jul 2008, Luis Machado wrote: > > > > This is a patch series to enable POWER7 VSX register set support in GDB. > > > > The VSX registers' layout is as follows: > > > > > > Will IBM be making appropriate proposals regarding these registers in the > > > Power.org ABI working group? The obvious things that need defining > > > include DWARF debug/unwind information handling of the registers, and > > > what's call-saved / call-clobbered, plus ABI handling of any new > > > C-language datatypes. > > > > Regarding call-saved / call-clobbered there's no option really. VSX > > registers follow the saved-ness of the registers they overlap with > > (either floating point or altivec). > > So will some of the bits that don't overlap be call-saved? If so, they > need setjmp/longjmp support and unwind support, including in the signal > unwind code in GCC. I presume such patches to the other toolchain > components will follow in due course if needed. No, those bits will be volatile, thus will be call-clobbered. As for the other toolchain components, probably there will be future patches to address the needed changes. For more information about the new register state: http://ozlabs.org/pipermail/linuxppc-dev/2008-June/058098.html Best regards, Luis