From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4059 invoked by alias); 6 Jun 2008 16:00:53 -0000 Received: (qmail 4017 invoked by uid 22791); 6 Jun 2008 16:00:49 -0000 X-Spam-Check-By: sourceware.org Received: from igw1.br.ibm.com (HELO igw1.br.ibm.com) (32.104.18.24) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 06 Jun 2008 16:00:28 +0000 Received: from mailhub1.br.ibm.com (mailhub1 [9.18.232.109]) by igw1.br.ibm.com (Postfix) with ESMTP id 1A89532C268 for ; Fri, 6 Jun 2008 12:35:06 -0300 (BRST) Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.18.232.47]) by mailhub1.br.ibm.com (8.13.8/8.13.8/NCO v9.0) with ESMTP id m56G0NMu888974 for ; Fri, 6 Jun 2008 13:00:24 -0300 Received: from d24av02.br.ibm.com (loopback [127.0.0.1]) by d24av02.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id m56G0Ix2008322 for ; Fri, 6 Jun 2008 13:00:19 -0300 Received: from [9.8.7.114] ([9.8.7.114]) by d24av02.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id m56G0GTF008208 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 Jun 2008 13:00:17 -0300 Subject: Re: [PATCH] PPC - Stepping off breakpoints in non-stop mode From: Luis Machado Reply-To: luisgpm@linux.vnet.ibm.com To: Daniel Jacobowitz Cc: Pedro Alves , gdb-patches@sourceware.org In-Reply-To: <20080605200249.GH25085@caradoc.them.org> References: <1209753019.7131.29.camel@gargoyle> <200805191422.49117.pedro@codesourcery.com> <1211203623.6232.2.camel@gargoyle> <1212020293.15367.63.camel@gargoyle> <20080605200249.GH25085@caradoc.them.org> Content-Type: text/plain Date: Fri, 06 Jun 2008 16:00:00 -0000 Message-Id: <1212768014.10042.60.camel@gargoyle> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-06/txt/msg00113.txt.bz2 On Thu, 2008-06-05 at 16:02 -0400, Daniel Jacobowitz wrote: > Sorry, the problem Pedro spotted is still there :-( How about the attached one? Best regards, Luis 2008-06-06 Luis Machado * ppc-tdep.h: Define PPC_MAX_INSN_LEN, BRANCH_MASK, B_INSN, BC_INSN, LWARX_MASK, LWARX_INSTRUCTION, LDARX_INSTRUCTION, STWCX_MASK, STWCX_INSTRUCTION, STDCX_INSTRUCTION, BXL_INSN, BP_MASK and BP_INSN. * rs6000-tdep.c (ppc_displaced_step_fixup): New function. (deal_with_atomic_sequence): Update BC masks. (rs6000_gdbarch_init): Init displaced stepping infra-structure. Remove LWARX_MASK, LWARX_INSTRUCTION, LDARX_INSTRUCTION, STWCX_MASK, STWCX_INSTRUCTION, STDCX_INSTRUCTION, BC_MASK and BC_INSTRUCTION. Index: gdb/ppc-tdep.h =================================================================== --- gdb.orig/ppc-tdep.h 2008-05-29 06:57:15.000000000 -0700 +++ gdb/ppc-tdep.h 2008-06-05 13:20:46.000000000 -0700 @@ -260,10 +260,28 @@ PPC_NUM_REGS }; +/* The length of the longest ppc instruction. */ +#define PPC_MAX_INSN_LEN (4) /* Instruction size. */ #define PPC_INSN_SIZE 4 +/* Instruction masks used during single-stepping of atomic sequences. */ +#define LWARX_MASK 0xfc0007fe +#define LWARX_INSTRUCTION 0x7c000028 +#define LDARX_INSTRUCTION 0x7c0000A8 +#define STWCX_MASK 0xfc0007ff +#define STWCX_INSTRUCTION 0x7c00012d +#define STDCX_INSTRUCTION 0x7c0001ad + +/* Instruction masks for displaced stepping. */ +#define BRANCH_MASK 0xfc000000 +#define BP_MASK 0xFC0007FE +#define B_INSN 0x48000000 +#define BC_INSN 0x40000000 +#define BXL_INSN 0x4c000000 +#define BP_INSN 0x7C000008 + /* Estimate for the maximum number of instrctions in a function epilogue. */ #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52 Index: gdb/rs6000-tdep.c =================================================================== --- gdb.orig/rs6000-tdep.c 2008-05-29 06:57:15.000000000 -0700 +++ gdb/rs6000-tdep.c 2008-06-06 07:20:28.000000000 -0700 @@ -841,16 +841,97 @@ return little_breakpoint; } +/* Fix up the state of registers and memory after having single-stepped + a displaced instruction. */ +void +ppc_displaced_step_fixup (struct gdbarch *gdbarch, + struct displaced_step_closure *closure, + CORE_ADDR from, CORE_ADDR to, + struct regcache *regs) +{ + /* Since we use simple_displaced_step_copy_insn, our closure is a + copy of the instruction. */ + ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure, + PPC_MAX_INSN_LEN); + ULONGEST opcode = 0; + LONGEST offset = PPC_MAX_INSN_LEN; /* Default offset for non PC-relative instructions. */ + + opcode = insn & BRANCH_MASK; + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, + "displaced: (ppc) fixup (0x%s, 0x%s)\n", + paddr_nz (from), paddr_nz (to)); + + + /* Handle PC-relative branch instructions. */ + if ((opcode == B_INSN) || (opcode == BC_INSN) || (opcode == BXL_INSN)) + { + /* LK bit Indicates whether we should set the link register to point + to the next instruction or not. */ + gdb_byte link_register_bit = (gdb_byte) (insn & 0x1); + CORE_ADDR current_pc; + + /* Read the current PC value after the instruction has been executed + in a displaced location. Calculate the offset to be applied to the + original PC value before the displaced stepping. */ + regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), + ¤t_pc); + offset = current_pc - to; + + if (opcode != BXL_INSN) + { + /* AA bit indicating whether this is an absolute addressing or + PC-relative. */ + gdb_byte absolute_addr_bit = (gdb_byte) (insn & 0x2); + + if (!absolute_addr_bit) + { -/* Instruction masks used during single-stepping of atomic sequences. */ -#define LWARX_MASK 0xfc0007fe -#define LWARX_INSTRUCTION 0x7c000028 -#define LDARX_INSTRUCTION 0x7c0000A8 -#define STWCX_MASK 0xfc0007ff -#define STWCX_INSTRUCTION 0x7c00012d -#define STDCX_INSTRUCTION 0x7c0001ad -#define BC_MASK 0xfc000000 -#define BC_INSTRUCTION 0x40000000 + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, + "displaced: (ppc) branch instruction: 0x%s\n" + "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n", + paddr_nz (insn), paddr_nz (current_pc), + paddr_nz (from + offset)); + + regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), + from + offset); + } + } + else + { + /* If we're here, it means we have a branch to LR or CTR. If the + branch was taken, the offset is probably greater than 4 (the next + instruction), so it's safe to assume that a offset of 4 means we + did not take the branch. */ + if (offset == PPC_MAX_INSN_LEN) + regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), + from + PPC_MAX_INSN_LEN); + } + + if (link_register_bit) + { + + regcache_cooked_write_unsigned (regs, + gdbarch_tdep (gdbarch)->ppc_lr_regnum, + from + PPC_MAX_INSN_LEN); + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, + "displaced: (ppc) adjusted LR to 0x%s\n", + paddr_nz (from + PPC_MAX_INSN_LEN)); + + } + } + /* Check for breakpoints in the inferior. If we've found one, place the PC + right at the breakpoint instruction. */ + else if ((insn & BP_MASK) == BP_INSN) + regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); + else + /* Handle any other instructions that do not fit in the categories above. */ + regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), + from + offset); +} /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX instruction and ending with a STWCX/STDCX instruction. If such a sequence @@ -887,7 +968,7 @@ /* Assume that there is at most one conditional branch in the atomic sequence. If a conditional branch is found, put a breakpoint in its destination address. */ - if ((insn & BC_MASK) == BC_INSTRUCTION) + if ((insn & BRANCH_MASK) == BC_INSN) { int immediate = ((insn & ~3) << 16) >> 16; int absolute = ((insn >> 1) & 1); @@ -3214,6 +3295,17 @@ /* Put the _Decimal128 pseudo-registers after the SPE registers. */ tdep->ppc_dl0_regnum += 32; + /* Setup displaced stepping. */ + set_gdbarch_displaced_step_copy_insn (gdbarch, + simple_displaced_step_copy_insn); + set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); + set_gdbarch_displaced_step_free_closure (gdbarch, + simple_displaced_step_free_closure); + set_gdbarch_displaced_step_location (gdbarch, + displaced_step_at_entry_point); + + set_gdbarch_max_insn_length (gdbarch, PPC_MAX_INSN_LEN); + return gdbarch; }