From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4279 invoked by alias); 10 May 2007 00:48:49 -0000 Received: (qmail 4271 invoked by uid 22791); 10 May 2007 00:48:49 -0000 X-Spam-Check-By: sourceware.org Received: from igw1.br.ibm.com (HELO igw1.br.ibm.com) (32.104.18.24) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 10 May 2007 00:48:46 +0000 Received: from mailhub1.br.ibm.com (mailhub1 [9.18.232.109]) by igw1.br.ibm.com (Postfix) with ESMTP id 3318214816E for ; Wed, 9 May 2007 21:37:22 -0300 (BRT) Received: from d24av01.br.ibm.com (d24av01.br.ibm.com [9.18.232.46]) by mailhub1.br.ibm.com (8.13.8/8.13.8/NCO v8.3) with ESMTP id l4A0mgKu1441826 for ; Wed, 9 May 2007 21:48:42 -0300 Received: from d24av01.br.ibm.com (loopback [127.0.0.1]) by d24av01.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id l4A0kdON019934 for ; Wed, 9 May 2007 21:46:40 -0300 Received: from [9.18.202.95] ([9.18.202.95]) by d24av01.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id l4A0kbo4019871; Wed, 9 May 2007 21:46:38 -0300 Subject: Re: [RFC] "single step" atomic instruction sequences as a whole on PPC From: Luis Machado Reply-To: luisgpm@linux.vnet.ibm.com To: Ulrich Weigand Cc: Daniel Jacobowitz , gdb-patches@sourceware.org In-Reply-To: <200705091945.l49Jjjf6030835@d12av02.megacenter.de.ibm.com> References: <200705091945.l49Jjjf6030835@d12av02.megacenter.de.ibm.com> Content-Type: multipart/mixed; boundary="=-KTf1Gqp1jFJmJ5wF/rV9" Date: Thu, 10 May 2007 00:48:00 -0000 Message-Id: <1178758118.16015.12.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.6.1 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-05/txt/msg00152.txt.bz2 --=-KTf1Gqp1jFJmJ5wF/rV9 Content-Type: text/plain Content-Transfer-Encoding: 7bit Content-length: 945 > I'd just do "opcode = insn >> 26" same as in rs6000_software_single_step. > (In fact I'm wondering why branch_dest doesn't just that for itself ...). Follows the updated patch. The "opcode" variable is now being assigned the correct instruction's opcode value (only the corresponding bits). As a consequence of this change, i've noticed problems with branch instructions next to the stwcx/stdcx instructions (the end of the sequence). Getting the destination address of this type of branch could potentially (upon a failing branch condition) lead to the function placing a breakpoint right at the stwcx/stdcx instruction, thus leading us back to the same locking problem. The variable "closing_insn" was created to check if the breakpoint at the branch instruction's destination is right at the stwcx/stdcx instruction. If so, ignore this breakpoint and consider only the breakpoint after the closing of the atomic sequence. Regards, Luis --=-KTf1Gqp1jFJmJ5wF/rV9 Content-Disposition: attachment; filename=fix_opcode_var.diff Content-Type: text/x-patch; name=fix_opcode_var.diff; charset=utf-8 Content-Transfer-Encoding: 7bit Content-length: 2322 2007-05-09 Luis Machado * rs6000-tdep.c: (deal_with_atomic_sequence) Stores branch instruction's opcode in the "opcode" variable and declares new variable "closing_insn". Index: gdb/rs6000-tdep.c =================================================================== --- gdb.orig/rs6000-tdep.c 2007-05-09 12:19:29.000000000 -0700 +++ gdb/rs6000-tdep.c 2007-05-09 17:36:13.000000000 -0700 @@ -729,12 +729,13 @@ CORE_ADDR breaks[2] = {-1, -1}; CORE_ADDR loc = pc; CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ + CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ int insn = read_memory_integer (loc, PPC_INSN_SIZE); int insn_count; int index; int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ - const int opcode = BC_INSTRUCTION; /* Branch instruction's OPcode. */ + int opcode; /* Branch instruction's OPcode. */ int bc_insn_count = 0; /* Conditional branch instruction count. */ /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ @@ -758,6 +759,7 @@ return 0; /* More than one conditional branch found, fallback to the standard single-step code. */ + opcode = insn >> 26; branch_bp = branch_dest (opcode, insn, pc, breaks[0]); if (branch_bp != -1) @@ -778,14 +780,19 @@ && (insn & STWCX_MASK) != STDCX_INSTRUCTION) return 0; + closing_insn = loc; loc += PPC_INSN_SIZE; insn = read_memory_integer (loc, PPC_INSN_SIZE); /* Insert a breakpoint right after the end of the atomic sequence. */ breaks[0] = loc; - /* Check for duplicated breakpoints. */ - if (last_breakpoint && (breaks[1] == breaks[0])) + /* Check for duplicated breakpoints. Check also for a breakpoint + placed (branch instruction's destination) at the stwcx/stdcx + instruction, this resets the reservation and take us back to the + lwarx/ldarx instruction at the beginning of the atomic sequence. */ + if (last_breakpoint && ((breaks[1] == breaks[0]) + || (breaks[1] == closing_insn))) last_breakpoint = 0; /* Effectively inserts the breakpoints. */ --=-KTf1Gqp1jFJmJ5wF/rV9--