From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22422 invoked by alias); 7 May 2007 15:14:04 -0000 Received: (qmail 22207 invoked by uid 22791); 7 May 2007 15:14:01 -0000 X-Spam-Check-By: sourceware.org Received: from igw1.br.ibm.com (HELO igw1.br.ibm.com) (32.104.18.24) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 07 May 2007 15:13:58 +0000 Received: from mailhub3.br.ibm.com (mailhub3 [9.18.232.110]) by igw1.br.ibm.com (Postfix) with ESMTP id C74B014801B for ; Mon, 7 May 2007 12:02:41 -0300 (BRT) Received: from d24av01.br.ibm.com (d24av01.br.ibm.com [9.18.232.46]) by mailhub3.br.ibm.com (8.13.8/8.13.8/NCO v8.3) with ESMTP id l47ElkQf913642 for ; Mon, 7 May 2007 12:13:51 -0300 Received: from d24av01.br.ibm.com (loopback [127.0.0.1]) by d24av01.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id l47E3UE6024624 for ; Mon, 7 May 2007 11:03:30 -0300 Received: from dyn531804.br.ibm.com (dyn531804.br.ibm.com [9.18.238.71]) by d24av01.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id l47E3Ub9024618; Mon, 7 May 2007 11:03:30 -0300 Subject: Re: [RFC] "single step" atomic instruction sequences as a whole on PPC From: Luis Machado Reply-To: luisgpm@linux.vnet.ibm.com To: Ulrich Weigand Cc: gdb-patches@sourceware.org In-Reply-To: <200705062120.l46LKf9l023985@d12av02.megacenter.de.ibm.com> References: <200705062120.l46LKf9l023985@d12av02.megacenter.de.ibm.com> Content-Type: multipart/mixed; boundary="=-Vv8Tv3YzBr/eRui8yrS6" Date: Mon, 07 May 2007 15:14:00 -0000 Message-Id: <1178546727.4427.3.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.6.1 X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-05/txt/msg00083.txt.bz2 --=-Vv8Tv3YzBr/eRui8yrS6 Content-Type: text/plain Content-Transfer-Encoding: 7bit Content-length: 574 Ulrich, > Thanks for the modifications. There's still a number of coding style > issues that I'll point out below. Thanks for the comments. I'm still getting used to the details of the coding standard. The patch has been updated. I hope i've addressed all the coding format issues this time. The handling of multiple conditional branches was modified so that when GDB finds such a situation it just silently falls back to the standard way of doing single-step. That way we won't have too much text on the screen in case this situation happens often. Best Regards, Luis --=-Vv8Tv3YzBr/eRui8yrS6 Content-Disposition: attachment; filename=ppc-atomic-single-stepping.diff Content-Type: text/x-patch; name=ppc-atomic-single-stepping.diff; charset=utf-8 Content-Transfer-Encoding: 7bit Content-length: 4849 2007-04-13 Luis Machado * rs6000-tdep.c: Defines masks for POWER instructions that set and use the reservation flag (LWARX,LDARX,STWCX,STDCX). * rs6000-tdep.c (deal_with_atomic_sequence): Handles single stepping through an atomic sequence of instructions. * rs6000-tdep.c (rs6000_software_single_step): Added a function call to check if we are stepping through an atomic sequence of instructions. * rs6000-tdep.c (rs6000_gdbarch_init): Initializes a function to check for atomic instruction sequences while single stepping. Index: gdb/rs6000-tdep.c =================================================================== --- gdb.orig/rs6000-tdep.c 2007-05-07 05:00:37.000000000 -0700 +++ gdb/rs6000-tdep.c 2007-05-07 06:57:27.000000000 -0700 @@ -706,8 +706,94 @@ return little_breakpoint; } +#define LWARX_MASK 0xfc0007fe +#define LWARX_INSTRUCTION 0x7c000028 +#define LDARX_INSTRUCTION 0x7c0000A8 +#define STWCX_MASK 0xfc0007ff +#define STWCX_INSTRUCTION 0x7c00012d +#define STDCX_INSTRUCTION 0x7c0001ad +#define BC_MASK 0xfc000000 +#define BC_INSTRUCTION 0x40000000 + +static int +deal_with_atomic_sequence (struct regcache *regcache) +{ + CORE_ADDR pc = read_pc (); + CORE_ADDR breaks[2] = {-1, -1}; + CORE_ADDR loc = pc; + CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ + int insn = read_memory_integer (loc, PPC_INSN_SIZE); + int insn_count; + int index; /* Index used for the "breaks" array. */ + int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ + const int atomic_sequence_length = 16; /* Instruction sequence length. */ + const int opcode = BC_INSTRUCTION; /* Branch instruction's OPcode. */ + int bc_insn_count = 0; /* Conditional branch instruction count. */ + + /* Assume all atomic sequences start with an lwarx or ldarx instruction. */ + if ((insn & LWARX_MASK) != LWARX_INSTRUCTION + && (insn & LWARX_MASK) != LDARX_INSTRUCTION) + return 0; + + /* Assume that no atomic sequence is longer than "atomic_sequence_length + instructions. */ + for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) + { + loc += PPC_INSN_SIZE; + insn = read_memory_integer (loc, PPC_INSN_SIZE); + + /* Assume that there is at most one conditional branch in the atomic + sequence. If a conditional branch is found, put a breakpoint in + its destination address. */ + if ((insn & BC_MASK) == BC_INSTRUCTION) + { + if (bc_insn_count >= 1) + return 0; /* More than one conditional branch found, fallback + to the standard single-step code. */ + + branch_bp = branch_dest (opcode, insn, pc, breaks[0]); + + if (branch_bp != -1) + { + breaks[1] = branch_bp; + bc_insn_count++; + last_breakpoint++; + } + } + + if ((insn & STWCX_MASK) == STWCX_INSTRUCTION + || (insn & STWCX_MASK) == STDCX_INSTRUCTION) + break; + } + + /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ + if ((insn & STWCX_MASK) != STWCX_INSTRUCTION + && (insn & STWCX_MASK) != STDCX_INSTRUCTION) + { + warning (_("Tried to step over an atomic sequence of instructions at %s\n \ + but could not find the end of the sequence."), + core_addr_to_string (pc)); + return 0; + } -/* AIX does not support PT_STEP. Simulate it. */ + loc += PPC_INSN_SIZE; + insn = read_memory_integer (loc, PPC_INSN_SIZE); + + /* Insert a breakpoint right after the end of the atomic sequence. */ + breaks[0] = loc; + + /* Check for duplicated breakpoints. */ + if (last_breakpoint && (breaks[1] == breaks[0])) + last_breakpoint = 0; + + /* Effectively inserts the breakpoints. */ + for (index = 0; index <= last_breakpoint; index++) + insert_single_step_breakpoint (breaks[index]); + + return 1; +} + +/* AIX does not support PT_STEP. Simulate it. */ int rs6000_software_single_step (struct regcache *regcache) @@ -724,6 +810,9 @@ insn = read_memory_integer (loc, 4); + if (deal_with_atomic_sequence (regcache)) + return 1; + breaks[0] = loc + breakp_sz; opcode = insn >> 26; breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); @@ -3448,6 +3537,9 @@ set_gdbarch_inner_than (gdbarch, core_addr_lessthan); set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); + /* Handles single stepping of atomic sequences */ + set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence); + /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" for the descriptor and ".FN" for the entry-point -- a user specifying "break FN" will unexpectedly end up with a breakpoint --=-Vv8Tv3YzBr/eRui8yrS6--