From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22602 invoked by alias); 22 Jun 2006 22:20:40 -0000 Received: (qmail 22580 invoked by uid 22791); 22 Jun 2006 22:20:38 -0000 X-Spam-Check-By: sourceware.org Received: from e2.ny.us.ibm.com (HELO e2.ny.us.ibm.com) (32.97.182.142) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 22 Jun 2006 22:20:31 +0000 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e2.ny.us.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id k5MMKS99003511 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Thu, 22 Jun 2006 18:20:29 -0400 Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay02.pok.ibm.com (8.13.6/NCO/VER7.0) with ESMTP id k5MMKSAp285594 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 22 Jun 2006 18:20:28 -0400 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id k5MMKSkQ026161 for ; Thu, 22 Jun 2006 18:20:28 -0400 Received: from dufur.beaverton.ibm.com (dufur.beaverton.ibm.com [9.47.22.20]) by d01av04.pok.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id k5MMKRQw026145 for ; Thu, 22 Jun 2006 18:20:28 -0400 Subject: Re: [patch] "single step" atomic instruction sequences as a whole. From: PAUL GILLIAM Reply-To: pgilliam@us.ibm.com To: gdb-patches@sourceware.org In-Reply-To: <1151009330.7608.68.camel@dufur.beaverton.ibm.com> References: <1151005894.7608.63.camel@dufur.beaverton.ibm.com> <1151009330.7608.68.camel@dufur.beaverton.ibm.com> Content-Type: multipart/mixed; boundary="=-sZ9LQCTAql4muH6d457e" Date: Thu, 22 Jun 2006 22:20:00 -0000 Message-Id: <1151010949.7608.71.camel@dufur.beaverton.ibm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.2.2 (2.2.2-5) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2006-06/txt/msg00341.txt.bz2 --=-sZ9LQCTAql4muH6d457e Content-Type: text/plain Content-Transfer-Encoding: 7bit Content-length: 758 On Thu, 2006-06-22 at 13:48 -0700, PAUL GILLIAM wrote: > On Thu, 2006-06-22 at 12:51 -0700, PAUL GILLIAM wrote: > > > You may ask "but what if an architecture needs the old > > software_single_step functionality *and* has sequences of instructions > > that need to be atomic?" > > It turns out, there *is* such an architecture and it can have the *same* > sequences instruction that need to be atomic as PPC: the RS6000! > > So here is a patch that adds dealing with atomic sequences for the > RS6000. > > The attach patch assumes that the 'change-software-single-step.diff' > patch has been applied. > > OK to commit? > > -=# Paul #=- Damn! I forget the change log entry... here is the patch for rs6000-tdep.c again. OK to commit? -=# Paul #=- --=-sZ9LQCTAql4muH6d457e Content-Disposition: attachment; filename=rs6000-atomic-single-step.diff Content-Type: text/x-patch; name=rs6000-atomic-single-step.diff; charset=utf-8 Content-Transfer-Encoding: 7bit Content-length: 3096 2006-06-22 Paul Gilliam * rs6000-tdep (deal_with_atomic_sequence): new (rs6000_software_single_step): Call the new routine to check for atomic sequences of instructions that need to be single stepped 'as a whole'. --- old_rs6000-tdep.c 2006-06-22 13:16:03.000000000 -0700 +++ rs6000-tdep.c 2006-06-22 13:41:10.000000000 -0700 @@ -701,8 +701,81 @@ return little_breakpoint; } +#define LWARX_MASK 0xfc0007fe +#define LWARX_INSTRUCTION 0x7C000028 +#define STWCX_MASK 0xfc0007ff +#define STWCX_INSTRUCTION 0x7c00012d +#define BC_MASK 0xfc000000 +#define BC_INSTRUCTION 0x40000000 +#define IMMEDIATE_PART(insn) (((insn & ~3) << 16) >> 16) +#define ABSOLUTE_P(insn) ((int) ((insn >> 1) & 1)) + +static int +deal_with_atomic_sequence (enum target_signal sig) +{ + CORE_ADDR pc = read_pc (); + CORE_ADDR breaks[2] = {-1, -1}; + CORE_ADDR loc = pc; + int insn = read_memory_integer (loc, 4); + int last_break = 0; + int i; + + + /* Assume all atomic sequences start with an lwarx instruction. */ + if ((insn & LWARX_MASK) != LWARX_INSTRUCTION) + return 0; -/* AIX does not support PT_STEP. Simulate it. */ + /* Assume that no atomic sequence is longer than 6 instructions. */ + for (i= 1; i < 5; ++i) + { + loc += PPC_INSN_SIZE; + insn = read_memory_integer (loc, 4); + + /* Assume at most one conditional branch instruction between + the lwarx and stwcx instructions.*/ + if ((insn & BC_MASK) == BC_INSTRUCTION) + { + last_break = 1; + breaks[1] = IMMEDIATE_PART (insn); + if ( ! ABSOLUTE_P(insn)) + breaks[1] += loc; + continue; + } + + if ((insn & STWCX_MASK) == STWCX_INSTRUCTION) + break; + } + + /* Assume that the atomic sequence ends with a stwcx instruction + followed by a conditional branch instruction. */ + if ((insn & STWCX_MASK) != STWCX_INSTRUCTION) + error (_("Tried to step over an atomic sequence of instructions but could not find the end of the sequence.")); + + loc += PPC_INSN_SIZE; + insn = read_memory_integer (loc, 4); + + if ((insn & BC_MASK) != BC_INSTRUCTION) + error (_("Tried to step over an atomic sequence of instructions but it did not end as expected.")); + + breaks[0] = loc; + + /* This should never happen, but make sure we don't but + two breakpoints on the same address. */ + if (last_break && breaks[1] == breaks[0]) + last_break = 0; + + for (i= 0; i < last_break; ++i) + insert_single_step_breakpoint (breaks[i]); + + printf_unfiltered (_("Stepping over an atomic sequence of instructions beginning at %s\n"), + core_addr_to_string (pc)); + gdb_flush (gdb_stdout); + + return 1; +} + +/* AIX does not support PT_STEP. Simulate it, dealing with any sequence of + instructions that must be atomic. */ int rs6000_software_single_step (enum target_signal signal, @@ -722,6 +795,9 @@ insn = read_memory_integer (loc, 4); + if (deal_with_atomic_sequence (signal)) + return 1; + breaks[0] = loc + breakp_sz; opcode = insn >> 26; breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); --=-sZ9LQCTAql4muH6d457e--