From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23261 invoked by alias); 9 Jun 2005 16:52:43 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 23230 invoked by uid 22791); 9 Jun 2005 16:52:32 -0000 Received: from alg145.algor.co.uk (HELO dmz.algor.co.uk) (62.254.210.145) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Thu, 09 Jun 2005 16:52:32 +0000 Received: from alg158.algor.co.uk ([62.254.210.158] helo=olympia.mips.com) by dmz.algor.co.uk with esmtp (Exim 3.35 #1 (Debian)) id 1DgQYn-0000GW-00 for ; Thu, 09 Jun 2005 18:11:17 +0100 Received: from stockwell.mips.com ([192.168.192.238]) by olympia.mips.com with esmtp (Exim 3.36 #1 (Debian)) id 1DgQGM-00007M-00 for ; Thu, 09 Jun 2005 17:52:14 +0100 Subject: [patch] MIPS16e support in simulator. From: David Ung To: gdb-patches@sources.redhat.com Content-Type: text/plain Date: Thu, 09 Jun 2005 16:52:00 -0000 Message-Id: <1118335933.1627.639.camel@localhost.localdomain> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTUK-Scanner: Found to be clean X-MTUK-SpamCheck: not spam (whitelisted), SpamAssassin (score=-4.846, required 4, AWL, BAYES_00) X-SW-Source: 2005-06/txt/msg00078.txt.bz2 This patch adds MIPS16e support in the GNU simulator. I've configure targets mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, mipsisa64r2*-*-* to generate both normal and mips16e code. David. 2005-06-09 David Ung Nigel Stephens * mips.igen: New mips16e model and include m16e.igen. (check_u64): Add mips16e tag. * m16e.igen: New file for MIPS16e instructions. * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e models. * configure: Regenerate. Index: src/sim/mips/mips.igen =================================================================== RCS file: /cvsroot/gcc/src-cvs/src/sim/mips/mips.igen,v retrieving revision 1.58 diff -c -p -b -r1.58 mips.igen *** src/sim/mips/mips.igen 26 May 2005 21:31:57 -0000 1.58 --- src/sim/mips/mips.igen 9 Jun 2005 16:48:28 -0000 *************** *** 68,73 **** --- 68,74 ---- // Instructions for the ASEs are in separate .igen files. // ASEs add instructions on to a base ISA. :model:::mips16:mips16: // m16.igen (and m16.dc) + :model:::mips16e:mips16e: // m16e.igen :model:::mips3d:mips3d: // mips3d.igen :model:::mdmx:mdmx: // mdmx.igen *************** *** 491,496 **** --- 492,498 ---- } :function:::void:check_u64:instruction_word insn + *mips16e: *mips64: *mips64r2: { *************** *** 5689,5694 **** --- 5691,5697 ---- :include:::mips3264r2.igen :include:::m16.igen + :include:::m16e.igen :include:::mdmx.igen :include:::mips3d.igen :include:::sb1.igen Index: src/sim/mips/configure.ac =================================================================== RCS file: /cvsroot/gcc/src-cvs/src/sim/mips/configure.ac,v retrieving revision 1.4 diff -c -p -b -r1.4 configure.ac *** src/sim/mips/configure.ac 26 May 2005 21:31:57 -0000 1.4 --- src/sim/mips/configure.ac 9 Jun 2005 16:49:05 -0000 *************** case "${target}" in *** 145,162 **** sim_igen_filter="32,64,f" sim_m16_filter="16" ;; ! mipsisa32r2*-*-*) sim_gen=IGEN ! sim_igen_machine="-M mips32r2" sim_igen_filter="32,f" sim_mach_default="mipsisa32r2" ;; ! mipsisa32*-*-*) sim_gen=IGEN ! sim_igen_machine="-M mips32" sim_igen_filter="32,f" sim_mach_default="mipsisa32" ;; ! mipsisa64r2*-*-*) sim_gen=IGEN ! sim_igen_machine="-M mips64r2,mips3d" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64r2" ;; --- 145,165 ---- sim_igen_filter="32,64,f" sim_m16_filter="16" ;; ! mipsisa32r2*-*-*) sim_gen=M16 ! sim_igen_machine="-M mips32r2,mips16,mips16e" ! sim_m16_machine="-M mips16,mips16e,mips32" sim_igen_filter="32,f" sim_mach_default="mipsisa32r2" ;; ! mipsisa32*-*-*) sim_gen=M16 ! sim_igen_machine="-M mips32,mips16,mips16e" ! sim_m16_machine="-M mips16,mips16e,mips32r2" sim_igen_filter="32,f" sim_mach_default="mipsisa32" ;; ! mipsisa64r2*-*-*) sim_gen=M16 ! sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e" ! sim_m16_machine="-M mips16,mips16e,mips64r2" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64r2" ;; *************** case "${target}" in *** 165,172 **** sim_igen_filter="32,64,f" sim_mach_default="mips_sb1" ;; ! mipsisa64*-*-*) sim_gen=IGEN ! sim_igen_machine="-M mips64,mips3d" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64" ;; --- 168,176 ---- sim_igen_filter="32,64,f" sim_mach_default="mips_sb1" ;; ! mipsisa64*-*-*) sim_gen=M16 ! sim_igen_machine="-M mips64,mips3d,mips16,mips16e" ! sim_m16_machine="-M mips16,mips16e,mips64" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64" ;; Index: src/sim/mips/m16e.igen =================================================================== // -*- C -*- // Simulator definition for the MIPS16e instructions. // Copyright (C) 2005 Free Software Foundation, Inc. // Contributed by Nigel Stephens (nigel@mips.com) and // David Ung (davidu@mips.com) of MIPS Technologies. // // This file is part of GDB, the GNU debugger. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License along // with this program; if not, write to the Free Software Foundation, Inc., // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 11101,3.RX,100,10001:RR:16::SEB "seb r" *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = EXTEND8 (GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,101,10001:RR:16::SEH "seh r" *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = EXTEND16 (GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,110,10001:RR:16::SEW "sew r" *mips16e: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = EXTEND32 (GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,000,10001:RR:16::ZEB "zeb r" *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,001,10001:RR:16::ZEH "zeh r" *mips16e: { TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,010,10001:RR:16::ZEW "zew r" *mips16e: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT1 (GPR[TRX]); GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]); TRACE_ALU_RESULT (GPR[TRX]); } 11101,3.RX,100,00000:RR:16::JRC "jrc r" *mips16e: { NIA = GPR[TRX]; } 11101,000,101,00000:RR:16::JRCRA "jrc ra" *mips16e: { NIA = RA; } 11101,3.RX,110,00000:RR:16::JALRC "jalrc r" *mips16e: { RA = NIA; NIA = GPR[TRX]; }