From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19198 invoked by alias); 29 Nov 2004 15:06:27 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 18826 invoked from network); 29 Nov 2004 15:05:59 -0000 Received: from unknown (HELO cam-admin0.cambridge.arm.com) (193.131.176.58) by sourceware.org with SMTP; 29 Nov 2004 15:05:59 -0000 Received: from pc960.cambridge.arm.com (pc960.cambridge.arm.com [10.1.205.4]) by cam-admin0.cambridge.arm.com (8.12.10/8.12.10) with ESMTP id iATF59mb007664; Mon, 29 Nov 2004 15:05:09 GMT Received: from pc960.cambridge.arm.com (localhost.localdomain [127.0.0.1]) by pc960.cambridge.arm.com (8.12.8/8.12.8) with ESMTP id iATF5vrg005187; Mon, 29 Nov 2004 15:05:57 GMT Received: (from rearnsha@localhost) by pc960.cambridge.arm.com (8.12.8/8.12.8/Submit) id iATF5vTm005185; Mon, 29 Nov 2004 15:05:57 GMT X-Authentication-Warning: pc960.cambridge.arm.com: rearnsha set sender to rearnsha@gcc.gnu.org using -f Subject: RE: [PATCH] Output execution stats from ARM simulator From: Richard Earnshaw To: jbeniston@compxs.com Cc: gdb-patches@sources.redhat.com In-Reply-To: <002301c4d623$6178e990$0bbda8c0@Kindrogan> References: <002301c4d623$6178e990$0bbda8c0@Kindrogan> Content-Type: text/plain Content-Transfer-Encoding: 7bit Organization: GNU Message-Id: <1101740756.1585.51.camel@pc960.cambridge.arm.com> Mime-Version: 1.0 Date: Mon, 29 Nov 2004 15:06:00 -0000 X-SW-Source: 2004-11/txt/msg00516.txt.bz2 On Mon, 2004-11-29 at 14:54, Jon Beniston wrote: > > > > > > 2004-11-29 Jon Beniston > > > > > > * wrapper.c (sim_info): Output number of instructions > > > executed and number of cycles taken to execute them. > > > > While I don't see anything wrong with your patch, I'm not > > sure whether that information is accurately tracked any more. > > So the numbers probably aren't meaningful, especially for > > any core other than an ARM7 (and I don't mean an ARM7TDMI either). > > I can understand cycles not being valid (as this surely is core specific), > but I take it the number of instructions executed should be? > > Cheers, > Jon A quick look at the source suggests the instruction count is probably OK in a free-running simulation, but I would want to do more testing for use with gdb and single-stepping before I could be certain about that case. The cycle counts are probably not modelled at all for some of the newly added instructions, and the S/N/I counts are pretty meaningless on Harvard-Architecture cores. R.