From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28729 invoked by alias); 1 Oct 2018 16:04:42 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 28449 invoked by uid 89); 1 Oct 2018 16:04:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=H*F:D*ca, it! X-HELO: smtp.polymtl.ca Received: from smtp.polymtl.ca (HELO smtp.polymtl.ca) (132.207.4.11) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Oct 2018 16:04:40 +0000 Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id w91G4XLw000979 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 1 Oct 2018 12:04:38 -0400 Received: by simark.ca (Postfix, from userid 112) id 48AB11E987; Mon, 1 Oct 2018 12:04:33 -0400 (EDT) Received: from simark.ca (localhost [127.0.0.1]) by simark.ca (Postfix) with ESMTP id 849F11E186; Mon, 1 Oct 2018 12:04:30 -0400 (EDT) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 01 Oct 2018 16:04:00 -0000 From: Simon Marchi To: "Metzger, Markus T" Cc: Simon Marchi , gdb-patches@sourceware.org Subject: Re: [PATCH] Fix is_amd64_regs_target check in i386-avx512.exp In-Reply-To: References: <20180928204114.20491-1-simon.marchi@ericsson.com> Message-ID: <109ef268e8076ad4b46fd6bb0b793432@polymtl.ca> X-Sender: simon.marchi@polymtl.ca User-Agent: Roundcube Webmail/1.3.6 X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00020.txt.bz2 On 2018-10-01 05:49, Metzger, Markus T wrote: > Hello Simon, > >> As reported by Jan here: >> >> https://sourceware.org/ml/gdb-patches/2018-09/msg00831.html >> >> the check that sets the number of available registers seems backwards. >> I can't test this patch however, since I don't have access to a cpu >> with AVX512. >> Could somebody perhaps from Intel, or somebody else that has access to >> such >> CPU, take a look? > > It indeed is backwards. > > The current test fails badly when run with -m32. > > >> gdb/testsuite/ChangeLog: >> >> * gdb.arch/i386-avx512.exp: Fix setting of nr_regs based on >> is_amd64_regs_target. >> --- >> gdb/testsuite/gdb.arch/i386-avx512.exp | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/gdb/testsuite/gdb.arch/i386-avx512.exp >> b/gdb/testsuite/gdb.arch/i386-avx512.exp >> index de2f62c3e1f..f27af534cfd 100644 >> --- a/gdb/testsuite/gdb.arch/i386-avx512.exp >> +++ b/gdb/testsuite/gdb.arch/i386-avx512.exp >> @@ -93,9 +93,9 @@ gdb_test "break [gdb_get_line_number "third >> breakpoint >> here"]" \ gdb_continue_to_breakpoint "continue to third breakpoint in >> main" >> >> if [is_amd64_regs_target] { >> - set nr_regs 8 >> -} else { >> set nr_regs 32 >> +} else { >> + set nr_regs 8 >> } >> >> for { set r 0 } { $r < $nr_regs } { incr r } { >> -- >> 2.19.0 > > With your patch, the test only fails for zmm registers due to broken > XSAVE > handling. This is fixed by Jan's patch. With both patches together, > the test > passes for -m32. Thanks a lot, I pushed it! Simon