From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26905 invoked by alias); 28 Sep 2004 10:04:35 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 26847 invoked from network); 28 Sep 2004 10:04:32 -0000 Received: from unknown (HELO mail03.idc.renesas.com) (202.234.163.13) by sourceware.org with SMTP; 28 Sep 2004 10:04:32 -0000 Received: (from root@localhost) by guardian03.idc.renesas.com with id i8SA4Hwu018245; Tue, 28 Sep 2004 19:04:17 +0900 (JST) Received: from unknown [172.20.8.70] by guardian03.idc.renesas.com with SMTP id VAA18242 ; Tue, 28 Sep 2004 19:04:17 +0900 Received: from mrkaisv.hoku.renesas.com ([10.145.105.245]) by rnsmtp01.hoku_r.renesas.com (8.9.3/3.7W) with ESMTP id TAA15608; Tue, 28 Sep 2004 19:04:15 +0900 (JST) Received: from E5A02646 (unknown [10.145.105.81]) by mrkaisv.hoku.renesas.com (Postfix) with SMTP id 055AD79809C; Tue, 28 Sep 2004 19:04:15 +0900 (JST) Message-ID: <01be01c4a542$82c7c010$5169910a@E5A02646> From: "Kei Sakamoto" To: "Mark Kettenis" Cc: References: <019601c49afa$1b78ce60$5169910a@E5A02646> <200409151125.i8FBPPCe013165@juw15.nfra.nl> Subject: [RFA/m32r] revised m32r-linux patch Date: Tue, 28 Sep 2004 10:04:00 -0000 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_01BB_01C4A58D.F2584760" X-SW-Source: 2004-09/txt/msg00451.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_01BB_01C4A58D.F2584760 Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: 7bit Content-length: 790 Hello, I revised the patch of m32r-linux support as you adviced. Linux/M32R kernel now supports PTRACE_GETREGS/SETREGS. So m32r-linux uses only PTRACE_GETREGS/SETREGS. I also replaced read_memory_unsigned_integer with safe_frame_unwind_memory . OK to commit? 2004-09-28 Kei Sakamoto Add m32r-linux support. * configure.tgt: Add m32r*-*-linux*. * Makefile.in (ALLDEPFILES): Add m32r-tdep.c, m32r-linux-nat.c and m32r-linux-tdep.c. (m32r-linux-nat.o, m32r-linux-tdep.o): New dependencies. * m32r-tdep.c: Move some definitions to m32r-tdep.h. * m32r-tdep.h, m32r-linux-nat.c, m32r-linux-tdep.c, config/m32r/linux.mh, config/m32r/linux.mt, config/m32r/m32r.mh, config/m32r/nm-linux.h, config/m32r/tm-linux.h: New files. ------=_NextPart_000_01BB_01C4A58D.F2584760 Content-Type: application/octet-stream; name="m32r-linux.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="m32r-linux.patch" Content-length: 33038 Index: Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/Makefile.in,v=0A= retrieving revision 1.629=0A= diff -a -u -r1.629 Makefile.in=0A= --- Makefile.in 27 Sep 2004 19:55:16 -0000 1.629=0A= +++ Makefile.in 28 Sep 2004 09:47:40 -0000=0A= @@ -719,6 +719,7 @@=0A= linespec_h =3D linespec.h=0A= linux_nat_h =3D linux-nat.h $(target_h)=0A= m2_lang_h =3D m2-lang.h=0A= +m32r_tdep_h =3D m32r-tdep.h=0A= m68k_tdep_h =3D m68k-tdep.h=0A= m88k_tdep_h =3D m88k-tdep.h=0A= macroexp_h =3D macroexp.h=0A= @@ -1381,6 +1382,8 @@=0A= libunwind-frame.c \=0A= lynx-nat.c m3-nat.c \=0A= m68hc11-tdep.c \=0A= + m32r-tdep.c \=0A= + m32r-linux-nat.c m32r-linux-tdep.c \=0A= m68k-tdep.c \=0A= m68kbsd-nat.c m68kbsd-tdep.c \=0A= m88k-tdep.c m88kbsd-nat.c \=0A= @@ -2137,15 +2140,21 @@=0A= $(expression_h) $(value_h) $(gdbcore_h) $(target_h) $(m2_lang_h)=0A= m2-valprint.o: m2-valprint.c $(defs_h) $(symtab_h) $(gdbtypes_h) \=0A= $(m2_lang_h)=0A= +m32r-linux-nat.o: m32r-linux-nat.c $(defs_h) $(inferior_h) $(gdbcore_h) \= =0A= + $(regcache_h) $(linux_nat_h) $(gdb_assert_h) $(gdb_string_h) \=0A= + $(m32r_tdep_h)=0A= +m32r-linux-tdep.o: m32r-linux-tdep.c $(defs_h) $(gdbcore_h) $(frame_h) \= =0A= + $(value_h) $(regcache_h) $(inferior_h) $(osabi_h) $(reggroups_h) \= =0A= + $(gdb_string_h) $(glibc_tdep_h) $(solib_svr4_h) $(m32r_tdep_h)=0A= m32r-rom.o: m32r-rom.c $(defs_h) $(gdbcore_h) $(target_h) $(monitor_h) \= =0A= - $(serial_h) $(symtab_h) $(command_h) $(gdbcmd_h) $(symfile_h) \=0A= - $(gdb_string_h) $(objfiles_h) $(inferior_h) $(regcache_h)=0A= + $(serial_h) $(symtab_h) $(command_h) $(gdbcmd_h) $(symfile_h) \=0A= + $(gdb_string_h) $(objfiles_h) $(inferior_h) $(regcache_h)=0A= m32r-stub.o: m32r-stub.c $(syscall_h)=0A= -m32r-tdep.o: m32r-tdep.c $(defs_h) $(frame_h) $(frame_unwind_h) \=0A= + m32r-tdep.o: m32r-tdep.c $(defs_h) $(frame_h) $(frame_unwind_h) \=0A= $(frame_base_h) $(symtab_h) $(gdbtypes_h) $(gdbcmd_h) $(gdbcore_h) \=0A= $(gdb_string_h) $(value_h) $(inferior_h) $(symfile_h) $(objfiles_h) \=0A= $(language_h) $(arch_utils_h) $(regcache_h) $(trad_frame_h) \=0A= - $(dis_asm_h) $(gdb_assert_h)=0A= + $(dis_asm_h) $(gdb_assert_h) $(m32r_tdep_h)=0A= m68hc11-tdep.o: m68hc11-tdep.c $(defs_h) $(frame_h) $(frame_unwind_h) \=0A= $(frame_base_h) $(dwarf2_frame_h) $(trad_frame_h) $(symtab_h) \=0A= $(gdbtypes_h) $(gdbcmd_h) $(gdbcore_h) $(gdb_string_h) $(value_h) \=0A= Index: configure.tgt=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/configure.tgt,v=0A= retrieving revision 1.146=0A= diff -a -u -r1.146 configure.tgt=0A= --- configure.tgt 12 Aug 2004 22:29:56 -0000 1.146=0A= +++ configure.tgt 28 Sep 2004 09:47:40 -0000=0A= @@ -106,7 +106,8 @@=0A= ;;=0A= ia64*-*-*) gdb_target=3Dia64 ;;=0A= =20=0A= -m32r-*-*) gdb_target=3Dm32r ;;=0A= +m32r*-*-linux*) gdb_target=3Dlinux ;;=0A= +m32r*-*-*) gdb_target=3Dm32r ;;=0A= =20=0A= m68hc11*-*-*|m6811*-*-*) gdb_target=3Dm68hc11 ;;=0A= =20=0A= Index: m32r-linux-nat.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: m32r-linux-nat.c=0A= diff -N m32r-linux-nat.c=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ m32r-linux-nat.c 28 Sep 2004 09:47:40 -0000=0A= @@ -0,0 +1,234 @@=0A= +/* Native-dependent code for GNU/Linux m32r.=0A= +=0A= + Copyright 2004 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 59 Temple Place - Suite 330,=0A= + Boston, MA 02111-1307, USA. */=0A= +=0A= +#include "defs.h"=0A= +#include "inferior.h"=0A= +#include "gdbcore.h"=0A= +#include "regcache.h"=0A= +#include "linux-nat.h"=0A= +=0A= +#include "gdb_assert.h"=0A= +#include "gdb_string.h"=0A= +#include =0A= +#include =0A= +#include =0A= +=0A= +/* Prototypes for supply_gregset etc. */=0A= +#include "gregset.h"=0A= +=0A= +#include "m32r-tdep.h"=0A= +=0A= +=0C=0A= +=0A= +=0A= +/* Since EVB register is not available for native debug, we reduce=0A= + the number of registers. */=0A= +#define M32R_LINUX_NUM_REGS (M32R_NUM_REGS - 1)=0A= +=0A= +/* Mapping between the general-purpose registers in `struct user'=0A= + format and GDB's register array layout. */=0A= +static int regmap[] =3D {=0A= + 4, 5, 6, 7, 0, 1, 2, 8,=0A= + 9, 10, 11, 12, 13, 24, 25, 23,=0A= + 19, 19, 26, 23, 22, 20, 16, 15=0A= +};=0A= +=0A= +#define PSW_REGMAP 19=0A= +#define BBPSW_REGMAP 21=0A= +#define SPU_REGMAP 23=0A= +#define SPI_REGMAP 26=0A= +=0A= +/* Doee apply to the corresponding SET requests as well. */=0A= +#define GETREGS_SUPPLIES(regno) (0 <=3D (regno) && (regno) <=3D M32R_LINUX= _NUM_REGS)=0A= +=0A= +=0C=0A= +=0A= +/* Transfering the general-purpose registers between GDB, inferiors=0A= + and core files. */=0A= +=0A= +/* Fill GDB's register array with the general-purpose register values=0A= + in *GREGSETP. */=0A= +=0A= +void=0A= +supply_gregset (elf_gregset_t * gregsetp)=0A= +{=0A= + elf_greg_t *regp =3D (elf_greg_t *) gregsetp;=0A= + int i;=0A= + unsigned long psw, bbpsw;=0A= +=0A= + psw =3D *(regp + PSW_REGMAP);=0A= + bbpsw =3D *(regp + BBPSW_REGMAP);=0A= +=0A= + for (i =3D 0; i < M32R_LINUX_NUM_REGS; i++)=0A= + {=0A= + switch (i)=0A= + {=0A= + case PSW_REGNUM:=0A= + *(regp + regmap[i]) =3D ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8)= ;=0A= + break;=0A= + case CBR_REGNUM:=0A= + *(regp + regmap[i]) =3D ((psw >> 8) & 1);=0A= + break;=0A= + }=0A= +=0A= + if (i !=3D M32R_SP_REGNUM)=0A= + regcache_raw_supply (current_regcache, i, regp + regmap[i]);=0A= + else if (psw & 0x8000)=0A= + regcache_raw_supply (current_regcache, i, regp + SPU_REGMAP);=0A= + else=0A= + regcache_raw_supply (current_regcache, i, regp + SPI_REGMAP);=0A= + }=0A= +}=0A= +=0A= +/* Fetch all general-purpose registers from process/thread TID and=0A= + store their values in GDB's register array. */=0A= +=0A= +static void=0A= +fetch_regs (int tid)=0A= +{=0A= + elf_gregset_t regs;=0A= +=0A= + if (ptrace (PTRACE_GETREGS, tid, 0, (int) ®s) < 0)=0A= + perror_with_name ("Couldn't get registers");=0A= +=0A= + supply_gregset (®s);=0A= +}=0A= +=0A= +/* Fill register REGNO (if it is a general-purpose register) in=0A= + *GREGSETPS with the value in GDB's register array. If REGNO is -1,=0A= + do this for all registers. */=0A= +=0A= +void=0A= +fill_gregset (elf_gregset_t * gregsetp, int regno)=0A= +{=0A= + elf_greg_t *regp =3D (elf_greg_t *) gregsetp;=0A= + int i;=0A= + unsigned long psw, bbpsw, tmp;=0A= +=0A= + psw =3D *(regp + PSW_REGMAP);=0A= + bbpsw =3D *(regp + BBPSW_REGMAP);=0A= +=0A= + for (i =3D 0; i < M32R_LINUX_NUM_REGS; i++)=0A= + {=0A= + if (regno !=3D -1 && regno !=3D i)=0A= + continue;=0A= +=0A= + if (i =3D=3D CBR_REGNUM || i =3D=3D PSW_REGNUM)=0A= + continue;=0A= +=0A= + if (i =3D=3D SPU_REGNUM || i =3D=3D SPI_REGNUM)=0A= + continue;=0A= +=0A= + if (i !=3D M32R_SP_REGNUM)=0A= + regcache_raw_collect (current_regcache, i, regp + regmap[i]);=0A= + else if (psw & 0x8000)=0A= + regcache_raw_collect (current_regcache, i, regp + SPU_REGMAP);=0A= + else=0A= + regcache_raw_collect (current_regcache, i, regp + SPI_REGMAP);=0A= + }=0A= +}=0A= +=0A= +/* Store all valid general-purpose registers in GDB's register array=0A= + into the process/thread specified by TID. */=0A= +=0A= +static void=0A= +store_regs (int tid, int regno)=0A= +{=0A= + elf_gregset_t regs;=0A= +=0A= + if (ptrace (PTRACE_GETREGS, tid, 0, (int) ®s) < 0)=0A= + perror_with_name ("Couldn't get registers");=0A= +=0A= + fill_gregset (®s, regno);=0A= +=0A= + if (ptrace (PTRACE_SETREGS, tid, 0, (int) ®s) < 0)=0A= + perror_with_name ("Couldn't write registers");=0A= +}=0A= +=0A= +=0C=0A= +=0A= +/* Transfering floating-point registers between GDB, inferiors and cores.= =20=20=0A= + Since M32R has no floating-point registers, these functions do nothing.= */=0A= +=0A= +void=0A= +supply_fpregset (gdb_fpregset_t *fpregs)=0A= +{=0A= +}=0A= +=0A= +void=0A= +fill_fpregset (gdb_fpregset_t *fpregs, int regno)=0A= +{=0A= +}=0A= +=0A= +=0C=0A= +=0A= +/* Transferring arbitrary registers between GDB and inferior. */=0A= +=0A= +/* Fetch register REGNO from the child process. If REGNO is -1, do=0A= + this for all registers (including the floating point and SSE=0A= + registers). */=0A= +=0A= +void=0A= +fetch_inferior_registers (int regno)=0A= +{=0A= + int tid;=0A= +=0A= + /* GNU/Linux LWP ID's are process ID's. */=0A= + tid =3D TIDGET (inferior_ptid);=0A= + if (tid =3D=3D 0)=0A= + tid =3D PIDGET (inferior_ptid); /* Not a threaded program. */=0A= +=0A= + /* Use the PTRACE_GETREGS request whenever possible, since it=0A= + transfers more registers in one system call, and we'll cache the=0A= + results. */=0A= + if (regno =3D=3D -1 || GETREGS_SUPPLIES (regno))=0A= + {=0A= + fetch_regs (tid);=0A= + return;=0A= + }=0A= +=0A= + internal_error (__FILE__, __LINE__,=0A= + "Got request for bad register number %d.", regno);=0A= +}=0A= +=0A= +/* Store register REGNO back into the child process. If REGNO is -1,=0A= + do this for all registers (including the floating point and SSE=0A= + registers). */=0A= +void=0A= +store_inferior_registers (int regno)=0A= +{=0A= + int tid;=0A= +=0A= + /* GNU/Linux LWP ID's are process ID's. */=0A= + if ((tid =3D TIDGET (inferior_ptid)) =3D=3D 0)=0A= + tid =3D PIDGET (inferior_ptid); /* Not a threaded program. */=0A= +=0A= + /* Use the PTRACE_SETREGS request whenever possible, since it=0A= + transfers more registers in one system call. */=0A= + if (regno =3D=3D -1 || GETREGS_SUPPLIES (regno))=0A= + {=0A= + store_regs (tid, regno);=0A= + return;=0A= + }=0A= +=0A= + internal_error (__FILE__, __LINE__,=0A= + "Got request to store bad register number %d.", regno);=0A= +}=0A= Index: m32r-linux-tdep.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: m32r-linux-tdep.c=0A= diff -N m32r-linux-tdep.c=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ m32r-linux-tdep.c 28 Sep 2004 09:47:40 -0000=0A= @@ -0,0 +1,337 @@=0A= +/* Target-dependent code for GNU/Linux m32r.=0A= +=0A= + Copyright 2004 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 59 Temple Place - Suite 330,=0A= + Boston, MA 02111-1307, USA. */=0A= +=0A= +#include "defs.h"=0A= +#include "gdbcore.h"=0A= +#include "frame.h"=0A= +#include "value.h"=0A= +#include "regcache.h"=0A= +#include "inferior.h"=0A= +#include "osabi.h"=0A= +#include "reggroups.h"=0A= +=0A= +#include "gdb_string.h"=0A= +=0A= +#include "glibc-tdep.h"=0A= +#include "solib-svr4.h"=0A= +=0A= +#include "trad-frame.h"=0A= +#include "frame-unwind.h"=0A= +=0A= +#include "m32r-tdep.h"=0A= +=0C=0A= +=0A= +/* Recognizing signal handler frames. */=0A= +=0A= +/* GNU/Linux has two flavors of signals. Normal signal handlers, and=0A= + "realtime" (RT) signals. The RT signals can provide additional=0A= + information to the signal handler if the SA_SIGINFO flag is set=0A= + when establishing a signal handler using `sigaction'. It is not=0A= + unlikely that future versions of GNU/Linux will support SA_SIGINFO=0A= + for normal signals too. */=0A= +=0A= +/* When the m32r Linux kernel calls a signal handler and the=0A= + SA_RESTORER flag isn't set, the return address points to a bit of=0A= + code on the stack. This function returns whether the PC appears to=0A= + be within this bit of code.=0A= +=0A= + The instruction sequence for normal signals is=0A= + ldi r7, #__NR_sigreturn=0A= + trap #2=0A= + or 0x67 0x77 0x10 0xf2.=0A= +=0A= + Checking for the code sequence should be somewhat reliable, because=0A= + the effect is to call the system call sigreturn. This is unlikely=0A= + to occur anywhere other than in a signal trampoline.=0A= +=0A= + It kind of sucks that we have to read memory from the process in=0A= + order to identify a signal trampoline, but there doesn't seem to be=0A= + any other way. Therefore we only do the memory reads if no=0A= + function name could be identified, which should be the case since=0A= + the code is on the stack.=0A= +=0A= + Detection of signal trampolines for handlers that set the=0A= + SA_RESTORER flag is in general not possible. Unfortunately this is=0A= + what the GNU C Library has been doing for quite some time now.=0A= + However, as of version 2.1.2, the GNU C Library uses signal=0A= + trampolines (named __restore and __restore_rt) that are identical=0A= + to the ones used by the kernel. Therefore, these trampolines are=0A= + supported too. */=0A= +=0A= +static const unsigned char linux_sigtramp_code[] =3D=0A= +{=0A= + 0x67, 0x77, 0x10, 0xf2,=0A= +};=0A= +=0A= +/* If PC is in a sigtramp routine, return the address of the start of=0A= + the routine. Otherwise, return 0. */=0A= +=0A= +static CORE_ADDR=0A= +m32r_linux_sigtramp_start (CORE_ADDR pc, struct frame_info *next_frame)=0A= +{=0A= + unsigned char buf[4];=0A= +=0A= + /* We only recognize a signal trampoline if PC is at the start of=0A= + one of the instructions. We optimize for finding the PC at the=0A= + start of the instruction sequence, as will be the case when the=0A= + trampoline is not the first frame on the stack. We assume that=0A= + in the case where the PC is not at the start of the instruction=0A= + sequence, there will be a few trailing readable bytes on the=0A= + stack. */=0A= +=0A= + if (pc % 2 !=3D 0)=0A= + {=0A= + if (!safe_frame_unwind_memory (next_frame, pc, buf, 2))=0A= + return 0;=0A= +=0A= + if (memcmp (buf, linux_sigtramp_code, 2) =3D=3D 0)=0A= + pc -=3D 2;=0A= + else=0A= + return 0;=0A= + }=0A= +=0A= + if (!safe_frame_unwind_memory (next_frame, pc, buf, 4))=0A= + return 0;=0A= +=0A= + if (memcmp (buf, linux_sigtramp_code, 4) !=3D 0)=0A= + return 0;=0A= +=0A= + return pc;=0A= +}=0A= +=0A= +/* This function does the same for RT signals. Here the instruction=0A= + sequence is=0A= + ldi r7, #__NR_rt_sigreturn=0A= + trap #2=0A= + or 0x97 0xf0 0x00 0xad 0x10 0xf2 0xf0 0x00.=0A= +=0A= + The effect is to call the system call rt_sigreturn. */=0A= +=0A= +static const unsigned char linux_rt_sigtramp_code[] =3D=0A= +{=0A= + 0x97, 0xf0, 0x00, 0xad, 0x10, 0xf2, 0xf0, 0x00,=0A= +};=0A= +=0A= +/* If PC is in a RT sigtramp routine, return the address of the start=0A= + of the routine. Otherwise, return 0. */=0A= +=0A= +static CORE_ADDR=0A= +m32r_linux_rt_sigtramp_start (CORE_ADDR pc, struct frame_info *next_frame)= =0A= +{=0A= + unsigned char buf[4];=0A= +=0A= + /* We only recognize a signal trampoline if PC is at the start of=0A= + one of the instructions. We optimize for finding the PC at the=0A= + start of the instruction sequence, as will be the case when the=0A= + trampoline is not the first frame on the stack. We assume that=0A= + in the case where the PC is not at the start of the instruction=0A= + sequence, there will be a few trailing readable bytes on the=0A= + stack. */=0A= +=0A= + if (pc % 2 !=3D 0)=0A= + return 0;=0A= +=0A= + if (!safe_frame_unwind_memory (next_frame, pc, buf, 4))=0A= + return 0;=0A= +=0A= + if (memcmp (buf, linux_rt_sigtramp_code, 4) =3D=3D 0)=0A= + {=0A= + if (!safe_frame_unwind_memory (next_frame, pc + 4, buf, 4))=0A= + return 0;=0A= +=0A= + if (memcmp (buf, linux_rt_sigtramp_code + 4, 4) =3D=3D 0)=0A= + return pc;=0A= + }=0A= + else if (memcmp (buf, linux_rt_sigtramp_code + 4, 4) =3D=3D 0)=0A= + {=0A= + if (!safe_frame_unwind_memory (next_frame, pc - 4, buf, 4))=0A= + return 0;=0A= +=0A= + if (memcmp (buf, linux_rt_sigtramp_code, 4) =3D=3D 0)=0A= + return pc - 4;=0A= + }=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +static int=0A= +m32r_linux_pc_in_sigtramp (CORE_ADDR pc, char *name, struct frame_info *ne= xt_frame)=0A= +{=0A= + /* If we have NAME, we can optimize the search. The trampolines are=0A= + named __restore and __restore_rt. However, they aren't dynamically= =0A= + exported from the shared C library, so the trampoline may appear to= =0A= + be part of the preceding function. This should always be sigaction,= =0A= + __sigaction, or __libc_sigaction (all aliases to the same function). = */=0A= + if (name =3D=3D NULL || strstr (name, "sigaction") !=3D NULL)=0A= + return (m32r_linux_sigtramp_start (pc, next_frame) !=3D 0=0A= + || m32r_linux_rt_sigtramp_start (pc, next_frame) !=3D 0);=0A= +=0A= + return (strcmp ("__restore", name) =3D=3D 0=0A= + || strcmp ("__restore_rt", name) =3D=3D 0);=0A= +}=0A= +=0A= +/* From . */=0A= +static int m32r_linux_sc_reg_offset[] =3D {=0A= + 4 * 4, /* r0 */=0A= + 5 * 4, /* r1 */=0A= + 6 * 4, /* r2 */=0A= + 7 * 4, /* r3 */=0A= + 0 * 4, /* r4 */=0A= + 1 * 4, /* r5 */=0A= + 2 * 4, /* r6 */=0A= + 8 * 4, /* r7 */=0A= + 9 * 4, /* r8 */=0A= + 10 * 4, /* r9 */=0A= + 11 * 4, /* r10 */=0A= + 12 * 4, /* r11 */=0A= + 13 * 4, /* r12 */=0A= + 21 * 4, /* fp */=0A= + 22 * 4, /* lr */=0A= + -1 * 4, /* sp */=0A= + 16 * 4, /* psw */=0A= + -1 * 4, /* cbr */=0A= + 23 * 4, /* spi */=0A= + 20 * 4, /* spu */=0A= + 19 * 4, /* bpc */=0A= + 17 * 4, /* pc */=0A= + 15 * 4, /* accl */=0A= + 14 * 4 /* acch */=0A= +};=0A= +=0A= +struct m32r_frame_cache=0A= +{=0A= + CORE_ADDR base, pc;=0A= + struct trad_frame_saved_reg *saved_regs;=0A= +};=0A= +=0A= +static struct m32r_frame_cache *=0A= +m32r_linux_sigtramp_frame_cache (struct frame_info *next_frame,=0A= + void **this_cache)=0A= +{=0A= + struct m32r_frame_cache *cache;=0A= + CORE_ADDR sigcontext_addr, addr;=0A= + int regnum;=0A= +=0A= + if ((*this_cache) !=3D NULL)=0A= + return (*this_cache);=0A= + cache =3D FRAME_OBSTACK_ZALLOC (struct m32r_frame_cache);=0A= + (*this_cache) =3D cache;=0A= + cache->saved_regs =3D trad_frame_alloc_saved_regs (next_frame);=0A= +=0A= + cache->base =3D frame_unwind_register_unsigned (next_frame, M32R_SP_REGN= UM);=0A= + sigcontext_addr =3D cache->base + 4;=0A= +=0A= + cache->pc =3D frame_pc_unwind (next_frame);=0A= + addr =3D m32r_linux_sigtramp_start (cache->pc, next_frame);=0A= + if (addr =3D=3D 0)=0A= + {=0A= + /* If this is a RT signal trampoline, adjust SIGCONTEXT_ADDR=0A= + accordingly. */=0A= + addr =3D m32r_linux_rt_sigtramp_start (cache->pc, next_frame);=0A= + if (addr)=0A= + sigcontext_addr +=3D 128;=0A= + else=0A= + addr =3D frame_func_unwind (next_frame);=0A= + }=0A= + cache->pc =3D addr;=0A= +=0A= + cache->saved_regs =3D trad_frame_alloc_saved_regs (next_frame);=0A= +=0A= + for (regnum =3D 0; regnum < sizeof (m32r_linux_sc_reg_offset) / 4; regnu= m++)=0A= + {=0A= + if (m32r_linux_sc_reg_offset[regnum] >=3D 0)=0A= + cache->saved_regs[regnum].addr =3D=0A= + sigcontext_addr + m32r_linux_sc_reg_offset[regnum];=0A= + }=0A= +=0A= + return cache;=0A= +}=0A= +=0A= +static void=0A= +m32r_linux_sigtramp_frame_this_id (struct frame_info *next_frame,=0A= + void **this_cache,=0A= + struct frame_id *this_id)=0A= +{=0A= + struct m32r_frame_cache *cache =3D=0A= + m32r_linux_sigtramp_frame_cache (next_frame, this_cache);=0A= +=0A= + (*this_id) =3D frame_id_build (cache->base, cache->pc);=0A= +}=0A= +=0A= +static void=0A= +m32r_linux_sigtramp_frame_prev_register (struct frame_info *next_frame,=0A= + void **this_cache,=0A= + int regnum, int *optimizedp,=0A= + enum lval_type *lvalp,=0A= + CORE_ADDR *addrp,=0A= + int *realnump, void *valuep)=0A= +{=0A= + struct m32r_frame_cache *cache =3D=0A= + m32r_linux_sigtramp_frame_cache (next_frame, this_cache);=0A= +=0A= + trad_frame_get_prev_register (next_frame, cache->saved_regs, regnum,=0A= + optimizedp, lvalp, addrp, realnump, valuep);=0A= +}=0A= +=0A= +static const struct frame_unwind m32r_linux_sigtramp_frame_unwind =3D {=0A= + SIGTRAMP_FRAME,=0A= + m32r_linux_sigtramp_frame_this_id,=0A= + m32r_linux_sigtramp_frame_prev_register=0A= +};=0A= +=0A= +static const struct frame_unwind *=0A= +m32r_linux_sigtramp_frame_sniffer (struct frame_info *next_frame)=0A= +{=0A= + CORE_ADDR pc =3D frame_pc_unwind (next_frame);=0A= + char *name;=0A= +=0A= + find_pc_partial_function (pc, &name, NULL, NULL);=0A= + if (m32r_linux_pc_in_sigtramp (pc, name, next_frame))=0A= + return &m32r_linux_sigtramp_frame_unwind;=0A= +=0A= + return NULL;=0A= +}=0A= +=0A= +static void=0A= +m32r_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)=0A= +{=0A= + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch);=0A= +=0A= + /* Since EVB register is not available for native debug, we reduce=0A= + the number of registers. */=0A= + set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS - 1);=0A= +=0A= + frame_unwind_append_sniffer (gdbarch, m32r_linux_sigtramp_frame_sniffer)= ;=0A= +=0A= + /* GNU/Linux uses SVR4-style shared libraries. */=0A= + set_solib_svr4_fetch_link_map_offsets=0A= + (gdbarch, svr4_ilp32_fetch_link_map_offsets);=0A= +}=0A= +=0A= +/* Provide a prototype to silence -Wmissing-prototypes. */=0A= +extern void _initialize_m32r_linux_tdep (void);=0A= +=0A= +void=0A= +_initialize_m32r_linux_tdep (void)=0A= +{=0A= + gdbarch_register_osabi (bfd_arch_m32r, 0, GDB_OSABI_LINUX,=0A= + m32r_linux_init_abi);=0A= +}=0A= Index: m32r-tdep.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/m32r-tdep.c,v=0A= retrieving revision 1.30=0A= diff -a -u -r1.30 m32r-tdep.c=0A= --- m32r-tdep.c 2 Aug 2004 19:44:40 -0000 1.30=0A= +++ m32r-tdep.c 28 Sep 2004 09:47:41 -0000=0A= @@ -41,27 +41,7 @@=0A= =20=0A= #include "gdb_assert.h"=0A= =20=0A= -struct gdbarch_tdep=0A= -{=0A= - /* gdbarch target dependent data here. Currently unused for M32R. */=0A= -};=0A= -=0A= -/* m32r register names. */=0A= -=0A= -enum=0A= -{=0A= - R0_REGNUM =3D 0,=0A= - R3_REGNUM =3D 3,=0A= - M32R_FP_REGNUM =3D 13,=0A= - LR_REGNUM =3D 14,=0A= - M32R_SP_REGNUM =3D 15,=0A= - PSW_REGNUM =3D 16,=0A= - M32R_PC_REGNUM =3D 21,=0A= - /* m32r calling convention. */=0A= - ARG1_REGNUM =3D R0_REGNUM,=0A= - ARGN_REGNUM =3D R3_REGNUM,=0A= - RET1_REGNUM =3D R0_REGNUM,=0A= -};=0A= +#include "m32r-tdep.h"=0A= =20=0A= /* Local functions */=0A= =20=0A= @@ -238,18 +218,12 @@=0A= "evb"=0A= };=0A= =20=0A= -static int=0A= -m32r_num_regs (void)=0A= -{=0A= - return (sizeof (m32r_register_names) / sizeof (m32r_register_names[0]));= =0A= -}=0A= -=0A= static const char *=0A= m32r_register_name (int reg_nr)=0A= {=0A= if (reg_nr < 0)=0A= return NULL;=0A= - if (reg_nr >=3D m32r_num_regs ())=0A= + if (reg_nr >=3D M32R_NUM_REGS)=0A= return NULL;=0A= return m32r_register_names[reg_nr];=0A= }=0A= @@ -921,7 +895,7 @@=0A= set_gdbarch_write_pc (gdbarch, m32r_write_pc);=0A= set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);=0A= =20=0A= - set_gdbarch_num_regs (gdbarch, m32r_num_regs ());=0A= + set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);=0A= set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);=0A= set_gdbarch_register_name (gdbarch, m32r_register_name);=0A= set_gdbarch_register_type (gdbarch, m32r_register_type);=0A= Index: m32r-tdep.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: m32r-tdep.h=0A= diff -N m32r-tdep.h=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ m32r-tdep.h 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,52 @@=0A= +/* Target-dependent code for Renesas M32R, for GDB.=0A= +=20=0A= + Copyright 2004 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 59 Temple Place - Suite 330,=0A= + Boston, MA 02111-1307, USA. */=0A= +=0A= +#ifndef M32R_TDEP_H=0A= +#define M32R_TDEP_H=0A= +=0A= +struct gdbarch_tdep=0A= +{=0A= + /* gdbarch target dependent data here. Currently unused for M32R. */=0A= +};=0A= +=0A= +/* m32r register names. */=0A= +=0A= +enum m32r_regnum=0A= +{=0A= + R0_REGNUM =3D 0,=0A= + R3_REGNUM =3D 3,=0A= + M32R_FP_REGNUM =3D 13,=0A= + LR_REGNUM =3D 14,=0A= + M32R_SP_REGNUM =3D 15,=0A= + PSW_REGNUM =3D 16,=0A= + CBR_REGNUM =3D 17,=0A= + SPU_REGNUM =3D 18,=0A= + SPI_REGNUM =3D 19,=0A= + M32R_PC_REGNUM =3D 21,=0A= + /* m32r calling convention. */=0A= + ARG1_REGNUM =3D R0_REGNUM,=0A= + ARGN_REGNUM =3D R3_REGNUM,=0A= + RET1_REGNUM =3D R0_REGNUM,=0A= +};=0A= +=0A= +#define M32R_NUM_REGS 25=0A= +=0A= +#endif /* m32r-tdep.h */=0A= Index: config/m32r/linux.mh=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: config/m32r/linux.mh=0A= diff -N config/m32r/linux.mh=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ config/m32r/linux.mh 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,8 @@=0A= +# Host: M32R based machine running GNU/Linux=0A= +=0A= +NAT_FILE=3D nm-linux.h=0A= +NATDEPFILES=3D infptrace.o inftarg.o fork-child.o corelow.o \=0A= + m32r-linux-nat.o linux-proc.o gcore.o \=0A= + proc-service.o thread-db.o linux-nat.o=0A= +=0A= +LOADLIBES=3D -ldl -rdynamic=0A= Index: config/m32r/linux.mt=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: config/m32r/linux.mt=0A= diff -N config/m32r/linux.mt=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ config/m32r/linux.mt 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,6 @@=0A= +# Target: Renesas M32R running GNU/Linux=0A= +TDEPFILES=3D m32r-tdep.o m32r-linux-tdep.o remote-m32r-sdi.o glibc-tdep.o = solib.o solib-svr4.o solib-legacy.o=0A= +TM_FILE=3D tm-linux.h=0A= +=0A= +SIM_OBS =3D remote-sim.o=0A= +SIM =3D ../sim/m32r/libsim.a=0A= Index: config/m32r/m32r.mh=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: config/m32r/m32r.mh=0A= diff -N config/m32r/m32r.mh=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ config/m32r/m32r.mh 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,8 @@=0A= +# Host: M32R running GNU/Linux=0A= +=0A= +NAT_FILE=3D nm-linux.h=0A= +NATDEPFILES=3D infptrace.o inftarg.o fork-child.o corelow.o \=0A= + core-regset.o linux-proc.o gcore.o \=0A= + proc-service.o thread-db.o lin-lwp.o=0A= +=0A= +LOADLIBES =3D -ldl -rdynamic=0A= Index: config/m32r/nm-linux.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: config/m32r/nm-linux.h=0A= diff -N config/m32r/nm-linux.h=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ config/m32r/nm-linux.h 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,29 @@=0A= +/* Definitions to make GDB run on an M32R based machine under GNU/Linux.= =0A= + Copyright 2004 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 59 Temple Place - Suite 330,=0A= + Boston, MA 02111-1307, USA. */=0A= +=0A= +#ifndef NM_M32R_LINUX_H=0A= +#define NM_M32R_LINUX_H=0A= +=0A= +#include "config/nm-linux.h"=0A= +=0A= +/* Override copies of {fetch,store}_inferior_registers in infptrace.c. */= =0A= +#define FETCH_INFERIOR_REGISTERS=0A= +=0A= +#endif /* NM_M32R_LINUX_H */=0A= Index: config/m32r/tm-linux.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: config/m32r/tm-linux.h=0A= diff -N config/m32r/tm-linux.h=0A= --- /dev/null 1 Jan 1970 00:00:00 -0000=0A= +++ config/m32r/tm-linux.h 28 Sep 2004 09:47:41 -0000=0A= @@ -0,0 +1,29 @@=0A= +/* Target-specific definitions for GNU/Linux running on a Renesas=0A= + M32R.=20=0A= +=0A= + Copyright 2004 Free Software Foundation, Inc.=0A= +=0A= + This file is part of GDB.=0A= +=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 59 Temple Place - Suite 330,=0A= + Boston, MA 02111-1307, USA. */=0A= +=0A= +#ifndef TM_LINUX_H=0A= +#define TM_LINUX_H=0A= +=0A= +/* Pull in GNU/Linux generic defs. */=0A= +#include "config/tm-linux.h"=0A= +=0A= +#endif /* #ifndef TM_LINUX_H */=0A= ------=_NextPart_000_01BB_01C4A58D.F2584760--