From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5323 invoked by alias); 9 May 2003 09:52:06 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 5156 invoked from network); 9 May 2003 09:52:02 -0000 Received: from unknown (HELO mail03.idc.renesas.com) (202.234.163.13) by sources.redhat.com with SMTP; 9 May 2003 09:52:02 -0000 Received: from mail03.idc.renesas.com (localhost [127.0.0.1]) by mail03.idc.renesas.com with ESMTP id h499q0qE021952 for ; Fri, 9 May 2003 18:52:00 +0900 (JST) Received: from guardian02.idc.renesas.com ([172.20.8.133]) by mail03.idc.renesas.com with ESMTP id h499q010021949 for ; Fri, 9 May 2003 18:52:00 +0900 (JST) Received: (from root@localhost) by guardian02.idc.renesas.com with id h499q1jq028955 for gdb-patches@sources.redhat.com; Fri, 9 May 2003 18:52:01 +0900 (JST) Received: from unknown [172.20.8.71] by guardian02.idc.renesas.com with SMTP id UAA28954 ; Fri, 9 May 2003 18:52:00 +0900 Received: from mta04.idc.renesas.com (localhost [127.0.0.1]) by mta04.idc.renesas.com with ESMTP id h499pxfe017333 for ; Fri, 9 May 2003 18:51:59 +0900 (JST) Received: from rnsmtp01.hoku_r.renesas.com ([10.145.246.51]) by mta04.idc.renesas.com with ESMTP id h499pwxN017330 for ; Fri, 9 May 2003 18:51:58 +0900 (JST) Received: from mrkaisv.hoku.renesas.com ([10.145.105.245]) by rnsmtp01.hoku_r.renesas.com (8.9.3/3.7W) with ESMTP id SAA27752 for ; Fri, 9 May 2003 18:51:59 +0900 (JST) Received: from KEI (unknown [10.145.105.81]) by mrkaisv.hoku.renesas.com (Postfix) with SMTP id 70DAE7983DB for ; Fri, 9 May 2003 18:51:58 +0900 (JST) Message-ID: <016301c31610$aafb4e70$5169910a@KEI> From: "Kei Sakamoto" To: Subject: [PATCH] multi-arching m32r Date: Fri, 09 May 2003 09:52:00 -0000 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0160_01C3165C.1ABB2320" X-Priority: 3 X-MSMail-Priority: Normal X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 X-SW-Source: 2003-05/txt/msg00132.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0160_01C3165C.1ABB2320 Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: 7bit Content-length: 649 Hello, It seems that M32R is now obsoleted because it does not use GDB's multi-arch framework. So I made it fully multi-arched. I attached a patch file created from insight-5.3 source files. If there is something wrong with it, please let me know. Kei Sakamoto 2003-05-09 Kei Sakamoto Make m32r multi-arched. * configure.tgt: Mark m32r as multi-arched. * m32r-rom.c: Add several macros originaly included in config/m32r/tm-m32r.h. * m32r-tdep.c: Add functions for multi-arch support. * config/m32r/m32r.mt: Remove TM_FILE. * config/m32r/tm-m32r.h: Removed. ------=_NextPart_000_0160_01C3165C.1ABB2320 Content-Type: application/octet-stream; name="m32r-multi-arch.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="m32r-multi-arch.patch" Content-length: 34393 diff -Naur insight-5.3.orig/gdb/config/m32r/m32r.mt insight-5.3.new/gdb/con= fig/m32r/m32r.mt=0A= --- insight-5.3.orig/gdb/config/m32r/m32r.mt Sun May 5 00:52:39 2002=0A= +++ insight-5.3.new/gdb/config/m32r/m32r.mt Fri May 9 11:28:38 2003=0A= @@ -1,5 +1,4 @@=0A= # Target: Mitsubishi m32r processor=0A= TDEPFILES=3D m32r-tdep.o monitor.o m32r-rom.o dsrec.o=0A= -TM_FILE=3D tm-m32r.h=0A= SIM_OBS =3D remote-sim.o=0A= SIM =3D ../sim/m32r/libsim.a=0A= diff -Naur insight-5.3.orig/gdb/config/m32r/tm-m32r.h insight-5.3.new/gdb/c= onfig/m32r/tm-m32r.h=0A= --- insight-5.3.orig/gdb/config/m32r/tm-m32r.h Sat Aug 24 09:21:35 2002=0A= +++ insight-5.3.new/gdb/config/m32r/tm-m32r.h Thu Jan 1 09:00:00 1970=0A= @@ -1,234 +0,0 @@=0A= -/* Parameters for execution on a Mitsubishi m32r processor.=0A= - Copyright 1996, 1997 Free Software Foundation, Inc.=20=0A= -=0A= - This file is part of GDB.=0A= -=0A= - This program is free software; you can redistribute it and/or modify=0A= - it under the terms of the GNU General Public License as published by=0A= - the Free Software Foundation; either version 2 of the License, or=0A= - (at your option) any later version.=0A= -=0A= - This program is distributed in the hope that it will be useful,=0A= - but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= - GNU General Public License for more details.=0A= -=0A= - You should have received a copy of the GNU General Public License=0A= - along with this program; if not, write to the Free Software=0A= - Foundation, Inc., 59 Temple Place - Suite 330,=0A= - Boston, MA 02111-1307, USA. */=0A= -=0A= -#include "regcache.h"=0A= -=0A= -/* Used by mswin. */=0A= -#define TARGET_M32R 1=0A= -=0A= -/* mvs_check REGISTER_NAMES */=0A= -#define REGISTER_NAMES \=0A= -{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \=0A= - "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \=0A= - "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", \=0A= - /* "cond", "sm", "bsm", "ie", "bie", "bcarry", */ \=0A= -}=0A= -/* mvs_check NUM_REGS */=0A= -#define NUM_REGS 24=0A= -=0A= -/* mvs_check REGISTER_SIZE */=0A= -#define REGISTER_SIZE 4=0A= -/* mvs_check MAX_REGISTER_RAW_SIZE */=0A= -#define MAX_REGISTER_RAW_SIZE 4=0A= -=0A= -/* mvs_check *_REGNUM */=0A= -#define R0_REGNUM 0=0A= -#define STRUCT_RETURN_REGNUM 0=0A= -#define ARG0_REGNUM 0=0A= -#define ARGLAST_REGNUM 3=0A= -#define V0_REGNUM 0=0A= -#define V1_REGNUM 1=0A= -#define FP_REGNUM 13=0A= -#define RP_REGNUM 14=0A= -#define SP_REGNUM 15=0A= -#define PSW_REGNUM 16=0A= -#define CBR_REGNUM 17=0A= -#define SPI_REGNUM 18=0A= -#define SPU_REGNUM 19=0A= -#define BPC_REGNUM 20=0A= -#define PC_REGNUM 21=0A= -#define ACCL_REGNUM 22=0A= -#define ACCH_REGNUM 23=0A= -=0A= -/* mvs_check REGISTER_BYTES */=0A= -#define REGISTER_BYTES (NUM_REGS * 4)=0A= -=0A= -/* mvs_check REGISTER_VIRTUAL_TYPE */=0A= -#define REGISTER_VIRTUAL_TYPE(REG) builtin_type_int=0A= -=0A= -/* mvs_check REGISTER_BYTE */=0A= -#define REGISTER_BYTE(REG) ((REG) * 4)=0A= -/* mvs_check REGISTER_VIRTUAL_SIZE */=0A= -#define REGISTER_VIRTUAL_SIZE(REG) 4=0A= -/* mvs_check REGISTER_RAW_SIZE */=0A= -#define REGISTER_RAW_SIZE(REG) 4=0A= -=0A= -/* mvs_check MAX_REGISTER_VIRTUAL_SIZE */=0A= -#define MAX_REGISTER_VIRTUAL_SIZE 4=0A= -=0A= -/* mvs_check BREAKPOINT */=0A= -#define BREAKPOINT {0x10, 0xf1}=0A= -=0A= -/* mvs_no_check FUNCTION_START_OFFSET */=0A= -#define FUNCTION_START_OFFSET 0=0A= -=0A= -/* mvs_check DECR_PC_AFTER_BREAK */=0A= -#define DECR_PC_AFTER_BREAK 0=0A= -=0A= -/* mvs_check INNER_THAN */=0A= -#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))=0A= -=0A= -/* mvs_check SAVED_PC_AFTER_CALL */=0A= -#define SAVED_PC_AFTER_CALL(fi) read_register (RP_REGNUM)=0A= -=0A= -struct frame_info;=0A= -struct frame_saved_regs;=0A= -struct type;=0A= -struct value;=0A= -=0A= -/* Define other aspects of the stack frame.=20=0A= - We keep the offsets of all saved registers, 'cause we need 'em a lot!= =0A= - We also keep the current size of the stack frame, and whether=20=0A= - the frame pointer is valid (for frameless functions, and when we're=0A= - still in the prologue of a function with a frame) */=0A= -=0A= -/* mvs_check EXTRA_FRAME_INFO */=0A= -#define EXTRA_FRAME_INFO \=0A= - struct frame_saved_regs fsr; \=0A= - int framesize; \=0A= - int using_frame_pointer;=0A= -=0A= -=0A= -extern void m32r_init_extra_frame_info (struct frame_info *fi);=0A= -/* mvs_check INIT_EXTRA_FRAME_INFO */=0A= -#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) m32r_init_extra_frame_info (fi= )=0A= -/* mvs_no_check INIT_FRAME_PC */=0A= -#define INIT_FRAME_PC /* Not necessary */=0A= -=0A= -extern void=0A= -m32r_frame_find_saved_regs (struct frame_info *fi,=0A= - struct frame_saved_regs *regaddr);=0A= -=0A= -/* Put here the code to store, into a struct frame_saved_regs,=0A= - the addresses of the saved registers of frame described by FRAME_INFO.= =0A= - This includes special registers such as pc and fp saved in special=0A= - ways in the stack frame. sp is even more special:=0A= - the address we return for it IS the sp for the next frame. */=0A= -=0A= -/* mvs_check FRAME_FIND_SAVED_REGS */=0A= -#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \=0A= - m32r_frame_find_saved_regs(frame_info, &(frame_saved_regs))=0A= -=0A= -extern CORE_ADDR m32r_frame_chain (struct frame_info *fi);=0A= -/* mvs_check FRAME_CHAIN */=0A= -#define FRAME_CHAIN(fi) m32r_frame_chain (fi)=0A= -=0A= -#define FRAME_CHAIN_VALID(fp, frame) generic_file_frame_chain_valid (fp, f= rame)=0A= -=0A= -extern CORE_ADDR m32r_find_callers_reg (struct frame_info *fi, int regnum)= ;=0A= -extern CORE_ADDR m32r_frame_saved_pc (struct frame_info *);=0A= -/* mvs_check FRAME_SAVED_PC */=0A= -#define FRAME_SAVED_PC(fi) m32r_frame_saved_pc (fi)=0A= -=0A= -/* mvs_check DEPRECATED_EXTRACT_RETURN_VALUE */=0A= -#define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE, REGBUF, VALBUF) \=0A= - memcpy ((VALBUF), \=0A= - (char *)(REGBUF) + REGISTER_BYTE (V0_REGNUM) + \=0A= - ((TYPE_LENGTH (TYPE) > 4 ? 8 : 4) - TYPE_LENGTH (TYPE)), \=0A= - TYPE_LENGTH (TYPE))=0A= -=0A= -/* mvs_check DEPRECATED_STORE_RETURN_VALUE */=0A= -#define DEPRECATED_STORE_RETURN_VALUE(TYPE, VALBUF) \=0A= - write_register_bytes(REGISTER_BYTE (V0_REGNUM) + \=0A= - ((TYPE_LENGTH (TYPE) > 4 ? 8:4) - TYPE_LENGTH (TYPE)),\=0A= - (VALBUF), TYPE_LENGTH (TYPE));=0A= -=0A= -extern CORE_ADDR m32r_skip_prologue (CORE_ADDR pc);=0A= -/* mvs_check SKIP_PROLOGUE */=0A= -#define SKIP_PROLOGUE(pc) (m32r_skip_prologue (pc))=0A= -=0A= -/* mvs_no_check FRAME_ARGS_SKIP */=0A= -#define FRAME_ARGS_SKIP 0=0A= -=0A= -/* mvs_no_check FRAME_ARGS_ADDRESS */=0A= -#define FRAME_ARGS_ADDRESS(fi) ((fi)->frame)=0A= -/* mvs_no_check FRAME_LOCALS_ADDRESS */=0A= -#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)=0A= -/* mvs_no_check FRAME_NUM_ARGS */=0A= -#define FRAME_NUM_ARGS(fi) (-1)=0A= -=0A= -#define COERCE_FLOAT_TO_DOUBLE(formal, actual) (1)=0A= -=0A= -extern void m32r_write_sp (CORE_ADDR val);=0A= -#define TARGET_WRITE_SP m32r_write_sp=0A= -=0A= -=0A= -=0A= -=0A= -=0A= -=0A= -/* struct passing and returning stuff */=0A= -#define STORE_STRUCT_RETURN(STRUCT_ADDR, SP) \=0A= - write_register (0, STRUCT_ADDR)=0A= -=0A= -extern use_struct_convention_fn m32r_use_struct_convention;=0A= -#define USE_STRUCT_CONVENTION(GCC_P, TYPE) m32r_use_struct_convention (GCC= _P, TYPE)=0A= -=0A= -#define DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \=0A= - extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \=0A= - REGISTER_RAW_SIZE (V0_REGNUM))=0A= -=0A= -#define REG_STRUCT_HAS_ADDR(gcc_p,type) (TYPE_LENGTH (type) > 8)=0A= -=0A= -=0A= -/* generic dummy frame stuff */=0A= -=0A= -#define PUSH_DUMMY_FRAME generic_push_dummy_frame ()=0A= -#define PC_IN_CALL_DUMMY(PC, SP, FP) generic_pc_in_call_dummy (PC, SP, FP)= =0A= -=0A= -=0A= -/* target-specific dummy_frame stuff */=0A= -=0A= -extern struct frame_info *m32r_pop_frame (struct frame_info *frame);=0A= -/* mvs_check POP_FRAME */=0A= -#define POP_FRAME m32r_pop_frame (get_current_frame ())=0A= -=0A= -/* mvs_no_check STACK_ALIGN */=0A= -/* #define STACK_ALIGN(x) ((x + 3) & ~3) */=0A= -=0A= -extern CORE_ADDR m32r_push_return_address (CORE_ADDR, CORE_ADDR);=0A= -extern CORE_ADDR m32r_push_arguments (int nargs,=0A= - struct value **args,=0A= - CORE_ADDR sp,=0A= - unsigned char struct_return,=0A= - CORE_ADDR struct_addr);=0A= -=0A= -=0A= -=0A= -/* mvs_no_check PUSH_ARGUMENTS */=0A= -#define PUSH_ARGUMENTS(NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR) \=0A= - (m32r_push_arguments (NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR))=0A= -=0A= -#define PUSH_RETURN_ADDRESS(PC, SP) m32r_push_return_address (PC, SP)= =0A= -=0A= -/* override the standard get_saved_register function with=20=0A= - one that takes account of generic CALL_DUMMY frames */=0A= -#define GET_SAVED_REGISTER(raw_buffer, optimized, addrp, frame, regnum, lv= al) \=0A= - generic_get_saved_register (raw_buffer, optimized, addrp, frame, regn= um, lval)=0A= -=0A= -=0A= -#define USE_GENERIC_DUMMY_FRAMES 1=0A= -#define CALL_DUMMY {0}=0A= -#define CALL_DUMMY_LENGTH (0)=0A= -#define CALL_DUMMY_START_OFFSET (0)=0A= -#define CALL_DUMMY_BREAKPOINT_OFFSET (0)=0A= -#define FIX_CALL_DUMMY(DUMMY1, STARTADDR, FUNADDR, NARGS, ARGS, TYPE, GCCP= )=0A= -#define CALL_DUMMY_LOCATION AT_ENTRY_POINT=0A= -#define CALL_DUMMY_ADDRESS() entry_point_address ()=0A= diff -Naur insight-5.3.orig/gdb/configure.tgt insight-5.3.new/gdb/configure= .tgt=0A= --- insight-5.3.orig/gdb/configure.tgt Sun Oct 20 21:14:39 2002=0A= +++ insight-5.3.new/gdb/configure.tgt Fri May 9 11:27:57 2003=0A= @@ -303,6 +303,7 @@=0A= =20=0A= case "${gdb_target}" in=0A= d10v) gdb_multi_arch=3Dyes ;;=0A= +m32r) gdb_multi_arch=3Dyes ;;=0A= m68hc11) gdb_multi_arch=3Dyes ;;=0A= mn10300) gdb_multi_arch=3Dyes ;;=0A= x86-64linux) gdb_multi_arch=3Dyes ;;=0A= diff -Naur insight-5.3.orig/gdb/m32r-rom.c insight-5.3.new/gdb/m32r-rom.c= =0A= --- insight-5.3.orig/gdb/m32r-rom.c Mon Jun 11 01:25:51 2001=0A= +++ insight-5.3.new/gdb/m32r-rom.c Fri May 9 11:29:37 2003=0A= @@ -57,6 +57,14 @@=0A= static char *download_path; /* user-settable path for SREC files */=0A= =20=0A= =20=0A= +/* REGNUM */=0A= +#define PSW_REGNUM 16=0A= +#define SPI_REGNUM 18=0A= +#define SPU_REGNUM 19=0A= +#define ACCL_REGNUM 22=0A= +#define ACCH_REGNUM 23=0A= +=0A= +=0A= /*=20=0A= * Function: m32r_load_1 (helper function)=0A= */=0A= diff -Naur insight-5.3.orig/gdb/m32r-tdep.c insight-5.3.new/gdb/m32r-tdep.c= =0A= --- insight-5.3.orig/gdb/m32r-tdep.c Tue Jul 30 01:34:06 2002=0A= +++ insight-5.3.new/gdb/m32r-tdep.c Fri May 9 11:30:27 2003=0A= @@ -28,6 +28,67 @@=0A= #include "gdbcore.h"=0A= #include "symfile.h"=0A= #include "regcache.h"=0A= +#include "arch-utils.h"=0A= +=0A= +=0A= +struct gdbarch_tdep=0A= +{=0A= + /* gdbarch target dependent data here. Currently unused for M32R. */=0A= +};=0A= +=0A= +=0A= +#define ARG0_REGNUM 0=0A= +#define ARGLAST_REGNUM 3=0A= +#define RP_REGNUM 14=0A= +#define PSW_REGNUM 16=0A= +#define SPI_REGNUM 18=0A= +#define SPU_REGNUM 19=0A= +=0A= + char *m32r_register_names[] =3D=0A= +{=0A= + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",=0A= + "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",=0A= + "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",=0A= + "evb"=0A= +};=0A= +=0A= +static int=20=0A= +m32r_num_regs (void)=0A= +{=0A= + return (sizeof (m32r_register_names));=0A= +}=0A= +=0A= +static const char *=0A= +m32r_register_name (int reg_nr)=0A= +{=0A= + if (reg_nr < 0)=0A= + return NULL;=0A= + if (reg_nr >=3D (sizeof (m32r_register_names) / sizeof (*m32r_register_n= ames)))=0A= + return NULL;=0A= + return m32r_register_names[reg_nr];=0A= +}=0A= +=0A= +static CORE_ADDR=0A= +m32r_saved_pc_after_call (struct frame_info *frame)=0A= +{=0A= + return read_register (14);=0A= +}=0A= +=0A= +=0A= +/* Additional info used by the frame */=0A= +=0A= +struct frame_saved_regs=0A= +{=0A= + CORE_ADDR regs[(sizeof (m32r_register_names) / sizeof (*m32r_register_na= mes))];=0A= +};=0A= +=0A= +struct frame_extra_info=0A= +{=0A= + struct frame_saved_regs fsr;=0A= + int framesize;=0A= + int using_frame_pointer;=0A= +};=0A= +=0A= =20=0A= /* Function: m32r_use_struct_convention=0A= Return nonzero if call_function should allocate stack space for a=0A= @@ -38,16 +99,14 @@=0A= return (TYPE_LENGTH (type) > 8);=0A= }=0A= =20=0A= -/* Function: frame_find_saved_regs=0A= +/* Function: frame_init_saved_regs=0A= Return the frame_saved_regs structure for the frame.=0A= Doesn't really work for dummy frames, but it does pass back=0A= an empty frame_saved_regs, so I guess that's better than total failure = */=0A= =20=0A= void=0A= -m32r_frame_find_saved_regs (struct frame_info *fi,=0A= - struct frame_saved_regs *regaddr)=0A= +m32r_frame_init_saved_regs (struct frame_info *fi)=0A= {=0A= - memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs));=0A= }=0A= =20=0A= /* Turn this on if you want to see just how much instruction decoding=0A= @@ -95,7 +154,6 @@=0A= =20=0A= These instructions are scheduled like everything else, so you should st= op at=0A= the first branch instruction.=0A= -=0A= */=0A= =20=0A= /* This is required by skip prologue and by m32r_init_extra_frame_info.=20= =0A= @@ -106,7 +164,7 @@=0A= */=0A= =20=0A= static void=0A= -decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, CORE_ADDR *pl_e= ndptr, /* var parameter */=0A= +decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, CORE_ADDR *pl_e= ndptr,=0A= unsigned long *framelength, struct frame_info *fi,=0A= struct frame_saved_regs *fsr)=0A= {=0A= @@ -125,25 +183,28 @@=0A= =20=0A= for (current_pc =3D start_pc; current_pc < scan_limit; current_pc +=3D 2= )=0A= {=0A= -=0A= insn =3D read_memory_unsigned_integer (current_pc, 2);=0A= dump_insn ("insn-1", current_pc, insn); /* MTZ */=0A= =20=0A= /* If this is a 32 bit instruction, we dont want to examine its=0A= immediate data as though it were an instruction */=0A= if (current_pc & 0x02)=0A= - { /* Clear the parallel execution bit from 16 bit instruction */=0A= + {=0A= + /* Clear the parallel execution bit from 16 bit instruction */= =0A= if (maybe_one_more)=0A= - { /* The last instruction was a branch, usually terminates=0A= - the series, but if this is a parallel instruction,=0A= - it may be a stack framing instruction */=0A= + {=0A= + /* The last instruction was a branch, usually terminates=0A= + the series, but if this is a parallel instruction,=0A= + it may be a stack framing instruction */=0A= if (!(insn & 0x8000))=0A= {=0A= insn_debug (("Really done"));=0A= - break; /* nope, we are really done */=0A= + /* nope, we are really done */=0A= + break;=0A= }=0A= }=0A= - insn &=3D 0x7fff; /* decode this instruction further */=0A= + /* decode this instruction further */=0A= + insn &=3D 0x7fff;=0A= }=0A= else=0A= {=0A= @@ -186,9 +247,9 @@=0A= { /* st reg, @-sp */=0A= int regno;=0A= insn_debug (("push\n"));=0A= -#if 0 /* No, PUSH FP is not an indication that we will use a frame poin= ter. */=0A= +#if 0 /* No, PUSH FP is not an indication that we will use a frame pointer= . */=0A= if (((insn & 0xffff) =3D=3D 0x2d7f) && fi)=0A= - fi->using_frame_pointer =3D 1;=0A= + fi->extra_info->using_frame_pointer =3D 1;=0A= #endif=0A= framesize +=3D 4;=0A= #if 0=0A= @@ -227,12 +288,13 @@=0A= if (insn =3D=3D 0x1d8f)=0A= { /* mv fp, sp */=0A= if (fi)=0A= - fi->using_frame_pointer =3D 1; /* fp is now valid */=0A= + fi->extra_info->using_frame_pointer =3D 1; /* fp is now valid */=0A= insn_debug (("done fp found\n"));=0A= after_prologue =3D current_pc + 2;=0A= break; /* end of stack adjustments */=0A= }=0A= - if (insn =3D=3D 0x7000) /* Nop looks like a branch, continue explici= tly */=0A= + /* Nop looks like a branch, continue explicitly */=0A= + if (insn =3D=3D 0x7000)=0A= {=0A= insn_debug (("nop\n"));=0A= after_prologue =3D current_pc + 2;=0A= @@ -313,7 +375,6 @@=0A= =20=0A= if (sal.line !=3D 0 && sal.end <=3D func_end)=0A= {=0A= -=0A= insn_debug (("BP after prologue %08x\n", sal.end));=0A= func_end =3D sal.end;=0A= }=0A= @@ -377,43 +438,46 @@=0A= examine the prologue. */=0A= =20=0A= void=0A= -m32r_init_extra_frame_info (struct frame_info *fi)=0A= +m32r_init_extra_frame_info (int fromleaf, struct frame_info *fi)=0A= {=0A= int reg;=0A= =20=0A= if (fi->next)=0A= fi->pc =3D FRAME_SAVED_PC (fi->next);=0A= =20=0A= - memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs);=0A= + fi->extra_info =3D (struct frame_extra_info *)=0A= + frame_obstack_alloc (sizeof (struct frame_extra_info));=0A= +=0A= + memset (fi->extra_info->fsr.regs, '\000', sizeof fi->extra_info->fsr.reg= s);=0A= =20=0A= if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))=0A= {=0A= /* We need to setup fi->frame here because run_stack_dummy gets it w= rong=0A= by assuming it's always FP. */=0A= fi->frame =3D generic_read_register_dummy (fi->pc, fi->frame, SP_REG= NUM);=0A= - fi->framesize =3D 0;=0A= + fi->extra_info->framesize =3D 0;=0A= return;=0A= }=0A= else=0A= {=0A= - fi->using_frame_pointer =3D 0;=0A= - fi->framesize =3D m32r_scan_prologue (fi, &fi->fsr);=0A= + fi->extra_info->using_frame_pointer =3D 0;=0A= + fi->extra_info->framesize =3D m32r_scan_prologue (fi, &fi->extra_inf= o->fsr);=0A= =20=0A= if (!fi->next)=0A= - if (fi->using_frame_pointer)=0A= - {=0A= - fi->frame =3D read_register (FP_REGNUM);=0A= - }=0A= + if (fi->extra_info->using_frame_pointer)=0A= + fi->frame =3D read_register (FP_REGNUM);=0A= else=0A= fi->frame =3D read_register (SP_REGNUM);=0A= else=0A= - /* fi->next means this is not the innermost frame */ if (fi->using_frame_= pointer)=0A= + /* fi->next means this is not the innermost frame */=0A= + if (fi->extra_info->using_frame_pointer)=0A= /* we have an FP */=0A= - if (fi->next->fsr.regs[FP_REGNUM] !=3D 0) /* caller saved our FP */=0A= - fi->frame =3D read_memory_integer (fi->next->fsr.regs[FP_REGNUM], 4);= =0A= + if (fi->next->extra_info->fsr.regs[FP_REGNUM] !=3D 0) /* caller saved our= FP */=0A= + fi->frame =3D read_memory_integer (fi->next->extra_info->fsr.regs[FP_RE= GNUM], 4);=0A= for (reg =3D 0; reg < NUM_REGS; reg++)=0A= - if (fi->fsr.regs[reg] !=3D 0)=0A= - fi->fsr.regs[reg] =3D fi->frame + fi->framesize - fi->fsr.regs[reg];=0A= + if (fi->extra_info->fsr.regs[reg] !=3D 0)=0A= + fi->extra_info->fsr.regs[reg] =3D=0A= + fi->frame + fi->extra_info->framesize - fi->extra_info->fsr.re= gs[reg];=0A= }=0A= }=0A= =20=0A= @@ -434,20 +498,44 @@=0A= fi.pc =3D pc;=0A= =20=0A= /* Analyze the prolog and fill in the extra info. */=0A= - m32r_init_extra_frame_info (&fi);=0A= -=0A= + m32r_init_extra_frame_info (0, &fi);=0A= =20=0A= /* Results will tell us which type of frame it uses. */=0A= - if (fi.using_frame_pointer)=0A= - {=0A= - *reg =3D FP_REGNUM;=0A= - *offset =3D 0;=0A= - }=0A= + if (fi.extra_info->using_frame_pointer)=0A= + *reg =3D FP_REGNUM;=0A= else=0A= - {=0A= - *reg =3D SP_REGNUM;=0A= - *offset =3D 0;=0A= - }=0A= + *reg =3D SP_REGNUM;=0A= + *offset =3D 0;=0A= +}=0A= +=0A= +static int=0A= +m32r_reg_struct_has_addr (int gcc_p, struct type *type)=0A= +{=0A= + return (TYPE_LENGTH (type) > 8);=0A= +}=0A= +=0A= +static struct type *=0A= +m32r_register_virtual_type (int reg)=0A= +{=0A= + return builtin_type_int;=0A= +}=0A= +=0A= +static int=0A= +m32r_register_byte (int reg)=0A= +{=0A= + return (reg * 4);=0A= +}=0A= +=0A= +static int=0A= +m32r_register_virtual_size (int reg)=0A= +{=0A= + return 4;=0A= +}=0A= +=0A= +static int=0A= +m32r_register_raw_size (int reg)=0A= +{=0A= + return 4;=0A= }=0A= =20=0A= /* Function: find_callers_reg=0A= @@ -463,8 +551,8 @@=0A= for (; fi; fi =3D fi->next)=0A= if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))=0A= return generic_read_register_dummy (fi->pc, fi->frame, regnum);=0A= - else if (fi->fsr.regs[regnum] !=3D 0)=0A= - return read_memory_integer (fi->fsr.regs[regnum],=0A= + else if (fi->extra_info->fsr.regs[regnum] !=3D 0)=0A= + return read_memory_integer (fi->extra_info->fsr.regs[regnum],=0A= REGISTER_RAW_SIZE (regnum));=0A= return read_register (regnum);=0A= }=0A= @@ -482,26 +570,26 @@=0A= =20=0A= /* is this a dummy frame? */=0A= if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))=0A= - return fi->frame; /* dummy frame same as caller's frame */=0A= + return fi->frame; /* dummy frame same as caller's frame */=0A= =20=0A= /* is caller-of-this a dummy frame? */=0A= callers_pc =3D FRAME_SAVED_PC (fi); /* find out who called us: */=0A= fp =3D m32r_find_callers_reg (fi, FP_REGNUM);=0A= if (PC_IN_CALL_DUMMY (callers_pc, fp, fp))=0A= - return fp; /* dummy frame's frame may bear no relation to ours */=0A= + return fp; /* dummy frame's frame may bear no relation to ours */=0A= =20=0A= if (find_pc_partial_function (fi->pc, 0, &fn_start, 0))=0A= if (fn_start =3D=3D entry_point_address ())=0A= - return 0; /* in _start fn, don't chain further */=0A= - if (fi->framesize =3D=3D 0)=0A= + return 0; /* in _start fn, don't chain further */=0A= + if (fi->extra_info->framesize =3D=3D 0)=0A= {=0A= printf_filtered ("cannot determine frame size @ %s , pc(%s)\n",=0A= paddr (fi->frame),=0A= paddr (fi->pc));=0A= return 0;=0A= }=0A= - insn_debug (("m32rx frame %08x\n", fi->frame + fi->framesize));=0A= - return fi->frame + fi->framesize;=0A= + insn_debug (("m32rx frame %08x\n", fi->frame + fi->extra_info->framesize= ));=0A= + return fi->frame + fi->extra_info->framesize;=0A= }=0A= =20=0A= /* Function: push_return_address (pc)=0A= @@ -516,13 +604,11 @@=0A= return sp;=0A= }=0A= =20=0A= +/* Discard from the stack the innermost frame, restoring all saved=0A= + registers. */=0A= =20=0A= -/* Function: pop_frame=0A= - Discard from the stack the innermost frame,=0A= - restoring all saved registers. */=0A= -=0A= -struct frame_info *=0A= -m32r_pop_frame (struct frame_info *frame)=0A= +static void=0A= +do_m32r_pop_frame (struct frame_info *frame)=0A= {=0A= int regnum;=0A= =20=0A= @@ -531,9 +617,9 @@=0A= else=0A= {=0A= for (regnum =3D 0; regnum < NUM_REGS; regnum++)=0A= - if (frame->fsr.regs[regnum] !=3D 0)=0A= + if (frame->extra_info->fsr.regs[regnum] !=3D 0)=0A= write_register (regnum,=0A= - read_memory_integer (frame->fsr.regs[regnum], 4));=0A= + read_memory_integer (frame->extra_info->fsr.regs[regnum], 4));=0A= =20=0A= write_register (PC_REGNUM, FRAME_SAVED_PC (frame));=0A= write_register (SP_REGNUM, read_register (FP_REGNUM));=0A= @@ -543,7 +629,12 @@=0A= write_register (SPI_REGNUM, read_register (SP_REGNUM));=0A= }=0A= flush_cached_frames ();=0A= - return NULL;=0A= +}=0A= +=0A= +static void=0A= +m32r_pop_frame (void)=0A= +{=0A= + generic_pop_current_frame (do_m32r_pop_frame);=0A= }=0A= =20=0A= /* Function: frame_saved_pc=0A= @@ -562,7 +653,7 @@=0A= /* Function: push_arguments=0A= Setup the function arguments for calling a function in the inferior.=0A= =20=0A= - On the Mitsubishi M32R architecture, there are four registers (R0 to R3= )=0A= + On the Renesas M32R architecture, there are four registers (R0 to R3)= =0A= which are dedicated for passing function arguments. Up to the first=20= =0A= four arguments (depending on size) may go into these registers.=0A= The rest go on the stack.=0A= @@ -590,9 +681,9 @@=0A= the callee to copy the return value to. A pointer to this space is=0A= passed as an implicit first argument, always in R0. */=0A= =20=0A= -CORE_ADDR=0A= +static CORE_ADDR=0A= m32r_push_arguments (int nargs, struct value **args, CORE_ADDR sp,=0A= - unsigned char struct_return, CORE_ADDR struct_addr)=0A= + int struct_return, CORE_ADDR struct_addr)=0A= {=0A= int stack_offset, stack_alloc;=0A= int argreg;=0A= @@ -697,8 +788,252 @@=0A= write_register (SP_REGNUM, val);=0A= }=0A= =20=0A= +=0A= +/* BREAKPOINT */=0A= +#define M32R_BE_BREAKPOINT32 {0x10, 0xf1, 0x70, 0x00}=0A= +#define M32R_LE_BREAKPOINT32 {0xf1, 0x10, 0x00, 0x70}=0A= +#define M32R_BE_BREAKPOINT16 {0x10, 0xf1}=0A= +#define M32R_LE_BREAKPOINT16 {0xf1, 0x10}=0A= +=0A= +static int=0A= +m32r_memory_insert_breakpoint(CORE_ADDR addr, char *contents_cache)=0A= +{=0A= + int val;=0A= + unsigned char *bp;=0A= + int bplen;=0A= +=0A= + bplen =3D (addr & 3)? 2 : 4;=0A= +=0A= + /* Save the memory contents. */=0A= + val =3D target_read_memory (addr, contents_cache, bplen);=20=0A= + if (val !=3D 0) return val; /* return error */=0A= +=0A= + /* Determine appropriate breakpoint contents and size for this address. = */=0A= + if (TARGET_BYTE_ORDER =3D=3D BFD_ENDIAN_BIG) {=0A= + if (((addr & 3) =3D=3D 0) &&=0A= + ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT32;=0A= + bp =3D insn;=0A= + bplen =3D sizeof(insn);=0A= + } else {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT16;=0A= + bp =3D insn;=0A= + bplen =3D sizeof(insn);=0A= + }=0A= + } else { /* little-endian */=0A= + if (((addr & 3) =3D=3D 0) &&=0A= + ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) {=0A= + static unsigned char insn[] =3D M32R_LE_BREAKPOINT32;=0A= + bp =3D insn;=0A= + bplen =3D sizeof(insn);=0A= + } else {=0A= + static unsigned char insn[] =3D M32R_LE_BREAKPOINT16;=0A= + bp =3D insn;=0A= + bplen =3D sizeof(insn);=0A= + }=0A= + }=0A= + /* Write the breakpoint. */=0A= + val =3D target_write_memory (addr, (char *) bp, bplen);=0A= + return val;=0A= +}=0A= +=0A= +static int=0A= +m32r_memory_remove_breakpoint(CORE_ADDR addr, char *contents_cache)=0A= +{=0A= + int val;=0A= + int bplen;=0A= +=0A= + /* Determine appropriate breakpoint contents and size for this address. = */=0A= + if (TARGET_BYTE_ORDER =3D=3D BFD_ENDIAN_BIG) {=0A= + if (((addr & 3) =3D=3D 0) &&=0A= + ((contents_cache[0] & 0x80) || (contents_cache[2] & 0x80))) {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT32;=0A= + bplen =3D sizeof(insn);=0A= + } else {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT16;=0A= + bplen =3D sizeof(insn);=0A= + }=0A= + } else { /* little-endian */=0A= + if (((addr & 3) =3D=3D 0) &&=0A= + ((contents_cache[1] & 0x80) || (contents_cache[3] & 0x80))) {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT32;=0A= + bplen =3D sizeof(insn);=0A= + } else {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT16;=0A= + bplen =3D sizeof(insn);=0A= + }=0A= + }=0A= + /* Write contents. */=0A= + val =3D target_write_memory (addr, contents_cache, bplen);=0A= + return val;=0A= +}=0A= +=0A= +static const unsigned char *=0A= +m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)=0A= +{=0A= + unsigned char *bp;=0A= +=0A= + /* Determine appropriate breakpoint. */=0A= + if (TARGET_BYTE_ORDER =3D=3D BFD_ENDIAN_BIG)=0A= + {=0A= + if ((*pcptr & 3) =3D=3D 0)=0A= + {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT32;=0A= + bp =3D insn;=0A= + *lenptr =3D sizeof(insn);=0A= + }=0A= + else=0A= + {=0A= + static unsigned char insn[] =3D M32R_BE_BREAKPOINT16;=0A= + bp =3D insn;=0A= + *lenptr =3D sizeof(insn);=0A= + }=0A= + }=0A= + else=0A= + {=0A= + if ((*pcptr & 3) =3D=3D 0)=0A= + {=0A= + static unsigned char insn[] =3D M32R_LE_BREAKPOINT32;=0A= + bp =3D insn;=0A= + *lenptr =3D sizeof(insn);=0A= + }=0A= + else=0A= + {=0A= + static unsigned char insn[] =3D M32R_LE_BREAKPOINT16;=0A= + bp =3D insn;=0A= + *lenptr =3D sizeof(insn);=0A= + }=0A= + }=0A= +=0A= + return bp;=0A= +}=0A= +=0A= +=0A= +static void=0A= +m32r_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES],= =0A= + char *valbuf)=0A= +{=0A= + memcpy (valbuf,=0A= + regbuf + REGISTER_BYTE (0)=0A= + + ((TYPE_LENGTH (type) > 4 ? 8 : 4) - TYPE_LENGTH (type)),=0A= + TYPE_LENGTH (type));=0A= +}=0A= +=0A= +static void=0A= +m32r_store_return_value (struct type *type, char *valbuf)=0A= +{=0A= + write_register_bytes(REGISTER_BYTE (0) + ((TYPE_LENGTH (type) > 4 ? 8:4)= =0A= + - TYPE_LENGTH (type)),=0A= + valbuf, TYPE_LENGTH (type));=0A= +}=0A= +=0A= +static void=0A= +m32r_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)=0A= +{=0A= + write_register (0, addr);=0A= +}=0A= +=0A= +static CORE_ADDR=0A= +m32r_extract_struct_value_address (char *regbuf)=0A= +{=0A= + return (extract_address (regbuf + REGISTER_BYTE (0), REGISTER_RAW_SIZE (= 0)));=0A= +}=0A= +=0A= +=0A= +static gdbarch_init_ftype m32r_gdbarch_init;=0A= +=0A= +static struct gdbarch *=0A= +m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)= =0A= +{=0A= + static LONGEST m32r_call_dummy_words[] =3D { 0 };=0A= + struct gdbarch_tdep *tdep;=0A= + struct gdbarch *gdbarch;=0A= +=0A= + /* Find a candidate among the list of pre-declared architectures. */=0A= + arches =3D gdbarch_list_lookup_by_info (arches, &info);=0A= + if (arches !=3D NULL)=0A= + return arches->gdbarch;=0A= +=0A= + /* None found, create a new architecture from the information provided. = */=0A= + tdep =3D XMALLOC (struct gdbarch_tdep);=0A= + gdbarch =3D gdbarch_alloc (&info, tdep);=0A= +=0A= + /* Registers. */=0A= + set_gdbarch_num_regs (gdbarch, m32r_num_regs());=0A= + set_gdbarch_register_name (gdbarch, m32r_register_name);=0A= + set_gdbarch_register_size (gdbarch, 4);=0A= + set_gdbarch_register_bytes (gdbarch, 4 * m32r_num_regs());=0A= + set_gdbarch_register_byte (gdbarch, m32r_register_byte);=0A= + set_gdbarch_register_raw_size (gdbarch, m32r_register_raw_size);=0A= + set_gdbarch_max_register_raw_size (gdbarch, 4);=0A= + set_gdbarch_register_virtual_size (gdbarch, m32r_register_virtual_size);= =0A= + set_gdbarch_max_register_virtual_size (gdbarch, 4);=0A= + set_gdbarch_register_virtual_type (gdbarch, m32r_register_virtual_type);= =0A= + set_gdbarch_sp_regnum (gdbarch, 15);=0A= + set_gdbarch_pc_regnum (gdbarch, 21);=0A= + set_gdbarch_fp_regnum (gdbarch, 13);=0A= + set_gdbarch_write_sp (gdbarch, m32r_write_sp);=0A= +=0A= + /* Frame Info. */=0A= + set_gdbarch_get_saved_register (gdbarch, generic_unwind_get_saved_regist= er);=0A= + set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);= =0A= + set_gdbarch_inner_than (gdbarch, core_addr_lessthan);=0A= + set_gdbarch_saved_pc_after_call (gdbarch, m32r_saved_pc_after_call);=0A= + set_gdbarch_init_extra_frame_info (gdbarch, m32r_init_extra_frame_info);= =0A= + set_gdbarch_frame_init_saved_regs (gdbarch, m32r_frame_init_saved_regs);= =0A= + set_gdbarch_frame_chain (gdbarch, m32r_frame_chain);=0A= + set_gdbarch_frame_saved_pc (gdbarch, m32r_frame_saved_pc);=0A= + set_gdbarch_deprecated_extract_return_value (gdbarch, m32r_extract_retur= n_value);=0A= + set_gdbarch_deprecated_extract_struct_value_address=0A= + (gdbarch, m32r_extract_struct_value_address);=0A= + set_gdbarch_deprecated_store_return_value (gdbarch, m32r_store_return_va= lue);=0A= + set_gdbarch_store_struct_return (gdbarch, m32r_store_struct_return);=0A= + set_gdbarch_pop_frame (gdbarch, m32r_pop_frame);=0A= + set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);=0A= + set_gdbarch_frame_args_skip (gdbarch, 0);=0A= + set_gdbarch_frame_args_address (gdbarch, default_frame_address);=0A= + set_gdbarch_frame_locals_address (gdbarch, default_frame_address);=0A= + set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);=0A= +=0A= + /* Calling functions in the inferior from GDB. */=0A= + set_gdbarch_use_generic_dummy_frames (gdbarch, 1);=0A= + set_gdbarch_call_dummy_length (gdbarch, 0);=0A= + set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);=0A= + set_gdbarch_call_dummy_address (gdbarch, entry_point_address);=0A= + set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);=0A= + set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);=0A= + set_gdbarch_call_dummy_start_offset (gdbarch, 0);=0A= + set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);=0A= + set_gdbarch_call_dummy_words (gdbarch, m32r_call_dummy_words);=0A= + set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (m32r_call_dummy_wo= rds));=0A= + set_gdbarch_call_dummy_p (gdbarch, 1);=0A= + set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);=0A= + set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);=0A= + set_gdbarch_push_arguments (gdbarch, m32r_push_arguments);=0A= + set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);=0A= + set_gdbarch_push_return_address (gdbarch, m32r_push_return_address);=0A= + set_gdbarch_reg_struct_has_addr (gdbarch, m32r_reg_struct_has_addr);=0A= + set_gdbarch_use_struct_convention (gdbarch, m32r_use_struct_convention);= =0A= +=0A= + /* Breakpoints. */=0A= + set_gdbarch_decr_pc_after_break (gdbarch, 0);=0A= + set_gdbarch_function_start_offset (gdbarch, 0);=0A= + set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);=0A= + set_gdbarch_memory_insert_breakpoint (gdbarch, m32r_memory_insert_breakp= oint);=0A= + set_gdbarch_memory_remove_breakpoint (gdbarch, m32r_memory_remove_breakp= oint);=0A= +=0A= + /* Misc. */=0A= + set_gdbarch_coerce_float_to_double (gdbarch, standard_coerce_float_to_do= uble);=0A= +=0A= + return gdbarch;=0A= +}=0A= +=0A= +=0A= void=0A= _initialize_m32r_tdep (void)=0A= {=0A= + register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);=0A= +=0A= tm_print_insn =3D print_insn_m32r;=0A= }=0A= +=0A= ------=_NextPart_000_0160_01C3165C.1ABB2320--